Michal Simek | 6455ac0 | 2007-05-05 18:27:16 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 Michal Simek |
| 3 | * |
| 4 | * Michal SIMEK <monstr@monstr.eu> |
| 5 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | 6455ac0 | 2007-05-05 18:27:16 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | /* FSL macros */ |
| 10 | #define NGET(val, fslnum) \ |
| 11 | __asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val)); |
Michal Simek | ee1aced | 2007-05-08 14:39:11 +0200 | [diff] [blame] | 12 | |
Michal Simek | 6455ac0 | 2007-05-05 18:27:16 +0200 | [diff] [blame] | 13 | #define GET(val, fslnum) \ |
| 14 | __asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val)); |
Michal Simek | ee1aced | 2007-05-08 14:39:11 +0200 | [diff] [blame] | 15 | |
| 16 | #define NCGET(val, fslnum) \ |
| 17 | __asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val)); |
| 18 | |
| 19 | #define CGET(val, fslnum) \ |
| 20 | __asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val)); |
| 21 | |
Michal Simek | 6455ac0 | 2007-05-05 18:27:16 +0200 | [diff] [blame] | 22 | #define NPUT(val, fslnum) \ |
| 23 | __asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val)); |
Michal Simek | ee1aced | 2007-05-08 14:39:11 +0200 | [diff] [blame] | 24 | |
Michal Simek | 6455ac0 | 2007-05-05 18:27:16 +0200 | [diff] [blame] | 25 | #define PUT(val, fslnum) \ |
| 26 | __asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val)); |
Michal Simek | 603aa74 | 2007-05-07 17:11:09 +0200 | [diff] [blame] | 27 | |
Michal Simek | ee1aced | 2007-05-08 14:39:11 +0200 | [diff] [blame] | 28 | #define NCPUT(val, fslnum) \ |
| 29 | __asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val)); |
| 30 | |
| 31 | #define CPUT(val, fslnum) \ |
| 32 | __asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val)); |
| 33 | |
Michal Simek | 6455ac0 | 2007-05-05 18:27:16 +0200 | [diff] [blame] | 34 | /* CPU dependent */ |
Michal Simek | 3af398e | 2007-05-08 14:52:52 +0200 | [diff] [blame] | 35 | /* machine status register */ |
Michal Simek | ebf7b23 | 2007-05-08 15:57:43 +0200 | [diff] [blame] | 36 | #define MFS(val, reg) \ |
| 37 | __asm__ __volatile__ ("mfs %0," #reg :"=r" (val)); |
Michal Simek | 603aa74 | 2007-05-07 17:11:09 +0200 | [diff] [blame] | 38 | |
Michal Simek | ebf7b23 | 2007-05-08 15:57:43 +0200 | [diff] [blame] | 39 | #define MTS(val, reg) \ |
| 40 | __asm__ __volatile__ ("mts " #reg ", %0"::"r" (val)); |
Michal Simek | 3af398e | 2007-05-08 14:52:52 +0200 | [diff] [blame] | 41 | |
Michal Simek | 98c1979 | 2007-05-07 23:58:31 +0200 | [diff] [blame] | 42 | /* get return address from interrupt */ |
Michal Simek | 603aa74 | 2007-05-07 17:11:09 +0200 | [diff] [blame] | 43 | #define R14(val) \ |
| 44 | __asm__ __volatile__ ("addi %0, r14, 0":"=r" (val)); |
Michal Simek | 98c1979 | 2007-05-07 23:58:31 +0200 | [diff] [blame] | 45 | |
Michal Simek | ebf7b23 | 2007-05-08 15:57:43 +0200 | [diff] [blame] | 46 | #define NOP __asm__ __volatile__ ("nop"); |
| 47 | |
Michal Simek | 98c1979 | 2007-05-07 23:58:31 +0200 | [diff] [blame] | 48 | /* use machine status registe USE_MSR_REG */ |
Michal Simek | 736245c | 2011-02-07 10:30:45 +0100 | [diff] [blame] | 49 | #if XILINX_USE_MSR_INSTR == 1 |
Michal Simek | 98c1979 | 2007-05-07 23:58:31 +0200 | [diff] [blame] | 50 | #define MSRSET(val) \ |
| 51 | __asm__ __volatile__ ("msrset r0," #val ); |
| 52 | |
| 53 | #define MSRCLR(val) \ |
| 54 | __asm__ __volatile__ ("msrclr r0," #val ); |
| 55 | |
| 56 | #else |
| 57 | #define MSRSET(val) \ |
| 58 | { \ |
| 59 | register unsigned tmp; \ |
| 60 | __asm__ __volatile__ (" \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 61 | mfs %0, rmsr; \ |
Michal Simek | 98c1979 | 2007-05-07 23:58:31 +0200 | [diff] [blame] | 62 | ori %0, %0, "#val"; \ |
| 63 | mts rmsr, %0; \ |
| 64 | nop;" \ |
| 65 | : "=r" (tmp) \ |
| 66 | : "d" (val) \ |
| 67 | : "memory"); \ |
| 68 | } |
| 69 | |
| 70 | #define MSRCLR(val) \ |
| 71 | { \ |
| 72 | register unsigned tmp; \ |
| 73 | __asm__ __volatile__ (" \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 74 | mfs %0, rmsr; \ |
Michal Simek | 98c1979 | 2007-05-07 23:58:31 +0200 | [diff] [blame] | 75 | andi %0, %0, ~"#val"; \ |
| 76 | mts rmsr, %0; \ |
| 77 | nop;" \ |
| 78 | : "=r" (tmp) \ |
| 79 | : "d" (val) \ |
| 80 | : "memory"); \ |
| 81 | } |
| 82 | #endif |