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Mayuresh Chitale7df8a0c2025-01-06 13:04:04 +00001/* SPDX-License-Identifier: GPL-2.0-only */
2#ifndef _ASM_RISCV_HWCAP_H
3#define _ASM_RISCV_HWCAP_H
4
5#define RISCV_ISA_EXT_a ('a' - 'a')
6#define RISCV_ISA_EXT_c ('c' - 'a')
7#define RISCV_ISA_EXT_d ('d' - 'a')
8#define RISCV_ISA_EXT_f ('f' - 'a')
9#define RISCV_ISA_EXT_h ('h' - 'a')
10#define RISCV_ISA_EXT_i ('i' - 'a')
11#define RISCV_ISA_EXT_m ('m' - 'a')
12#define RISCV_ISA_EXT_q ('q' - 'a')
13#define RISCV_ISA_EXT_v ('v' - 'a')
14
15/*
16 * These macros represent the logical IDs of each multi-letter RISC-V ISA
17 * extension and are used in the ISA bitmap. The logical IDs start from
18 * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single
19 * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order
20 * to allocate the bitmap and may be increased when necessary.
21 *
22 * New extensions should just be added to the bottom, rather than added
23 * alphabetically, in order to avoid unnecessary shuffling.
24 */
25#define RISCV_ISA_EXT_BASE 26
26
27#define RISCV_ISA_EXT_SSCOFPMF 26
28#define RISCV_ISA_EXT_SSTC 27
29#define RISCV_ISA_EXT_SVINVAL 28
30#define RISCV_ISA_EXT_SVPBMT 29
31#define RISCV_ISA_EXT_ZBB 30
32#define RISCV_ISA_EXT_ZICBOM 31
33#define RISCV_ISA_EXT_ZIHINTPAUSE 32
34#define RISCV_ISA_EXT_SVNAPOT 33
35#define RISCV_ISA_EXT_ZICBOZ 34
36#define RISCV_ISA_EXT_SMAIA 35
37#define RISCV_ISA_EXT_SSAIA 36
38#define RISCV_ISA_EXT_ZBA 37
39#define RISCV_ISA_EXT_ZBS 38
40#define RISCV_ISA_EXT_ZICNTR 39
41#define RISCV_ISA_EXT_ZICSR 40
42#define RISCV_ISA_EXT_ZIFENCEI 41
43#define RISCV_ISA_EXT_ZIHPM 42
44#define RISCV_ISA_EXT_SMSTATEEN 43
45#define RISCV_ISA_EXT_ZICOND 44
46#define RISCV_ISA_EXT_ZBC 45
47#define RISCV_ISA_EXT_ZBKB 46
48#define RISCV_ISA_EXT_ZBKC 47
49#define RISCV_ISA_EXT_ZBKX 48
50#define RISCV_ISA_EXT_ZKND 49
51#define RISCV_ISA_EXT_ZKNE 50
52#define RISCV_ISA_EXT_ZKNH 51
53#define RISCV_ISA_EXT_ZKR 52
54#define RISCV_ISA_EXT_ZKSED 53
55#define RISCV_ISA_EXT_ZKSH 54
56#define RISCV_ISA_EXT_ZKT 55
57#define RISCV_ISA_EXT_ZVBB 56
58#define RISCV_ISA_EXT_ZVBC 57
59#define RISCV_ISA_EXT_ZVKB 58
60#define RISCV_ISA_EXT_ZVKG 59
61#define RISCV_ISA_EXT_ZVKNED 60
62#define RISCV_ISA_EXT_ZVKNHA 61
63#define RISCV_ISA_EXT_ZVKNHB 62
64#define RISCV_ISA_EXT_ZVKSED 63
65#define RISCV_ISA_EXT_ZVKSH 64
66#define RISCV_ISA_EXT_ZVKT 65
67#define RISCV_ISA_EXT_ZFH 66
68#define RISCV_ISA_EXT_ZFHMIN 67
69#define RISCV_ISA_EXT_ZIHINTNTL 68
70#define RISCV_ISA_EXT_ZVFH 69
71#define RISCV_ISA_EXT_ZVFHMIN 70
72#define RISCV_ISA_EXT_ZFA 71
73#define RISCV_ISA_EXT_ZTSO 72
74#define RISCV_ISA_EXT_ZACAS 73
75#define RISCV_ISA_EXT_ZVE32X 74
76#define RISCV_ISA_EXT_ZVE32F 75
77#define RISCV_ISA_EXT_ZVE64X 76
78#define RISCV_ISA_EXT_ZVE64F 77
79#define RISCV_ISA_EXT_ZVE64D 78
80#define RISCV_ISA_EXT_ZIMOP 79
81#define RISCV_ISA_EXT_ZCA 80
82#define RISCV_ISA_EXT_ZCB 81
83#define RISCV_ISA_EXT_ZCD 82
84#define RISCV_ISA_EXT_ZCF 83
85#define RISCV_ISA_EXT_ZCMOP 84
86#define RISCV_ISA_EXT_ZAWRS 85
87#define RISCV_ISA_EXT_SVVPTC 86
88#define RISCV_ISA_EXT_SMMPM 87
89#define RISCV_ISA_EXT_SMNPM 88
90#define RISCV_ISA_EXT_SSNPM 89
91
92#define RISCV_ISA_EXT_XLINUXENVCFG 127
93
94#define RISCV_ISA_EXT_MAX 128
95#define RISCV_ISA_EXT_INVALID U32_MAX
96
97#ifdef CONFIG_RISCV_M_MODE
98#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA
99#define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SMNPM
100#else
101#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
102#define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SSNPM
103#endif
104
105#endif /* _ASM_RISCV_HWCAP_H */