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Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated
4 * Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
5 */
6
7#include <clk.h>
8#include <dm.h>
Svyatoslav Ryhela7ae9882025-02-21 13:29:43 +02009#include <dm/ofnode_graph.h>
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +020010#include <i2c.h>
11#include <log.h>
12#include <mipi_display.h>
13#include <mipi_dsi.h>
14#include <backlight.h>
15#include <panel.h>
Svyatoslav Ryhel73091cc2025-02-14 15:28:28 +020016#include <video_bridge.h>
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +020017#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/kernel.h>
20#include <linux/math64.h>
21#include <power/regulator.h>
22
23#include <asm/gpio.h>
24
25/* Global (16-bit addressable) */
26#define TC358768_CHIPID 0x0000
27#define TC358768_SYSCTL 0x0002
28#define TC358768_CONFCTL 0x0004
29#define TC358768_VSDLY 0x0006
30#define TC358768_DATAFMT 0x0008
31#define TC358768_GPIOEN 0x000E
32#define TC358768_GPIODIR 0x0010
33#define TC358768_GPIOIN 0x0012
34#define TC358768_GPIOOUT 0x0014
35#define TC358768_PLLCTL0 0x0016
36#define TC358768_PLLCTL1 0x0018
37#define TC358768_CMDBYTE 0x0022
38#define TC358768_PP_MISC 0x0032
39#define TC358768_DSITX_DT 0x0050
40#define TC358768_FIFOSTATUS 0x00F8
41
42/* Debug (16-bit addressable) */
43#define TC358768_VBUFCTRL 0x00E0
44#define TC358768_DBG_WIDTH 0x00E2
45#define TC358768_DBG_VBLANK 0x00E4
46#define TC358768_DBG_DATA 0x00E8
47
48/* TX PHY (32-bit addressable) */
49#define TC358768_CLW_DPHYCONTTX 0x0100
50#define TC358768_D0W_DPHYCONTTX 0x0104
51#define TC358768_D1W_DPHYCONTTX 0x0108
52#define TC358768_D2W_DPHYCONTTX 0x010C
53#define TC358768_D3W_DPHYCONTTX 0x0110
54#define TC358768_CLW_CNTRL 0x0140
55#define TC358768_D0W_CNTRL 0x0144
56#define TC358768_D1W_CNTRL 0x0148
57#define TC358768_D2W_CNTRL 0x014C
58#define TC358768_D3W_CNTRL 0x0150
59
60/* TX PPI (32-bit addressable) */
61#define TC358768_STARTCNTRL 0x0204
62#define TC358768_DSITXSTATUS 0x0208
63#define TC358768_LINEINITCNT 0x0210
64#define TC358768_LPTXTIMECNT 0x0214
65#define TC358768_TCLK_HEADERCNT 0x0218
66#define TC358768_TCLK_TRAILCNT 0x021C
67#define TC358768_THS_HEADERCNT 0x0220
68#define TC358768_TWAKEUP 0x0224
69#define TC358768_TCLK_POSTCNT 0x0228
70#define TC358768_THS_TRAILCNT 0x022C
71#define TC358768_HSTXVREGCNT 0x0230
72#define TC358768_HSTXVREGEN 0x0234
73#define TC358768_TXOPTIONCNTRL 0x0238
74#define TC358768_BTACNTRL1 0x023C
75
76/* TX CTRL (32-bit addressable) */
77#define TC358768_DSI_CONTROL 0x040C
78#define TC358768_DSI_STATUS 0x0410
79#define TC358768_DSI_INT 0x0414
80#define TC358768_DSI_INT_ENA 0x0418
81#define TC358768_DSICMD_RDFIFO 0x0430
82#define TC358768_DSI_ACKERR 0x0434
83#define TC358768_DSI_ACKERR_INTENA 0x0438
84#define TC358768_DSI_ACKERR_HALT 0x043c
85#define TC358768_DSI_RXERR 0x0440
86#define TC358768_DSI_RXERR_INTENA 0x0444
87#define TC358768_DSI_RXERR_HALT 0x0448
88#define TC358768_DSI_ERR 0x044C
89#define TC358768_DSI_ERR_INTENA 0x0450
90#define TC358768_DSI_ERR_HALT 0x0454
91#define TC358768_DSI_CONFW 0x0500
92#define TC358768_DSI_LPCMD 0x0500
93#define TC358768_DSI_RESET 0x0504
94#define TC358768_DSI_INT_CLR 0x050C
95#define TC358768_DSI_START 0x0518
96
97/* DSITX CTRL (16-bit addressable) */
98#define TC358768_DSICMD_TX 0x0600
99#define TC358768_DSICMD_TYPE 0x0602
100#define TC358768_DSICMD_WC 0x0604
101#define TC358768_DSICMD_WD0 0x0610
102#define TC358768_DSICMD_WD1 0x0612
103#define TC358768_DSICMD_WD2 0x0614
104#define TC358768_DSICMD_WD3 0x0616
105#define TC358768_DSI_EVENT 0x0620
106#define TC358768_DSI_VSW 0x0622
107#define TC358768_DSI_VBPR 0x0624
108#define TC358768_DSI_VACT 0x0626
109#define TC358768_DSI_HSW 0x0628
110#define TC358768_DSI_HBPR 0x062A
111#define TC358768_DSI_HACT 0x062C
112
113/* TC358768_DSI_CONTROL (0x040C) register */
114#define TC358768_DSI_CONTROL_DIS_MODE BIT(15)
115#define TC358768_DSI_CONTROL_TXMD BIT(7)
116#define TC358768_DSI_CONTROL_HSCKMD BIT(5)
117#define TC358768_DSI_CONTROL_EOTDIS BIT(0)
118
119/* TC358768_DSI_CONFW (0x0500) register */
120#define TC358768_DSI_CONFW_MODE_SET (5 << 29)
121#define TC358768_DSI_CONFW_MODE_CLR (6 << 29)
122#define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (3 << 24)
123
124#define NANO 1000000000UL
125#define PICO 1000000000000ULL
126
127struct tc358768_priv {
128 struct mipi_dsi_host host;
129 struct mipi_dsi_device device;
130
131 struct udevice *panel;
132 struct display_timing timing;
133
134 struct udevice *vddc;
135 struct udevice *vddmipi;
136 struct udevice *vddio;
137
138 struct clk *refclk;
139
140 struct gpio_desc reset_gpio;
141
142 u32 pd_lines; /* number of Parallel Port Input Data Lines */
143 u32 dsi_lanes; /* number of DSI Lanes */
144
145 /* Parameters for PLL programming */
146 u32 fbd; /* PLL feedback divider */
147 u32 prd; /* PLL input divider */
148 u32 frs; /* PLL Freqency range for HSCK (post divider) */
149
150 u32 dsiclk; /* pll_clk / 2 */
151};
152
153static void tc358768_read(struct udevice *dev, u32 reg, u32 *val)
154{
155 int count;
156 u8 buf[4] = { 0, 0, 0, 0 };
157
158 /* 16-bit register? */
159 if (reg < 0x100 || reg >= 0x600)
160 count = 2;
161 else
162 count = 4;
163
164 dm_i2c_read(dev, reg, buf, count);
165 *val = (buf[0] << 8) | (buf[1] & 0xff) |
166 (buf[2] << 24) | (buf[3] << 16);
167
168 log_debug("%s 0x%04x >> 0x%08x\n",
169 __func__, reg, *val);
170}
171
172static void tc358768_write(struct udevice *dev, u32 reg, u32 val)
173{
174 int count;
175 u8 buf[4];
176
177 /* 16-bit register? */
178 if (reg < 0x100 || reg >= 0x600)
179 count = 2;
180 else
181 count = 4;
182
183 buf[0] = val >> 8;
184 buf[1] = val & 0xff;
185 buf[2] = val >> 24;
186 buf[3] = val >> 16;
187
188 log_debug("%s 0x%04x << 0x%08x\n",
189 __func__, reg, val);
190
191 dm_i2c_write(dev, reg, buf, count);
192}
193
194static void tc358768_update_bits(struct udevice *dev, u32 reg, u32 mask,
195 u32 val)
196{
197 u32 tmp, orig;
198
199 tc358768_read(dev, reg, &orig);
200
201 tmp = orig & ~mask;
202 tmp |= val & mask;
203 if (tmp != orig)
204 tc358768_write(dev, reg, tmp);
205}
206
207static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host,
208 const struct mipi_dsi_msg *msg)
209{
210 struct udevice *dev = (struct udevice *)host->dev;
211 struct mipi_dsi_packet packet;
212 int ret;
213
214 if (msg->rx_len) {
215 log_debug("%s: MIPI rx is not supported\n", __func__);
216 return -EOPNOTSUPP;
217 }
218
219 if (msg->tx_len > 8) {
220 log_debug("%s: Maximum 8 byte MIPI tx is supported\n", __func__);
221 return -EOPNOTSUPP;
222 }
223
224 ret = mipi_dsi_create_packet(&packet, msg);
225 if (ret)
226 return ret;
227
228 if (mipi_dsi_packet_format_is_short(msg->type)) {
229 tc358768_write(dev, TC358768_DSICMD_TYPE,
230 (0x10 << 8) | (packet.header[0] & 0x3f));
231 tc358768_write(dev, TC358768_DSICMD_WC, 0);
232 tc358768_write(dev, TC358768_DSICMD_WD0,
233 (packet.header[2] << 8) | packet.header[1]);
234 } else {
235 int i;
236
237 tc358768_write(dev, TC358768_DSICMD_TYPE,
238 (0x40 << 8) | (packet.header[0] & 0x3f));
239 tc358768_write(dev, TC358768_DSICMD_WC, packet.payload_length);
240 for (i = 0; i < packet.payload_length; i += 2) {
241 u16 val = packet.payload[i];
242
243 if (i + 1 < packet.payload_length)
244 val |= packet.payload[i + 1] << 8;
245
246 tc358768_write(dev, TC358768_DSICMD_WD0 + i, val);
247 }
248 }
249
250 /* start transfer */
251 tc358768_write(dev, TC358768_DSICMD_TX, 1);
252
253 return packet.size;
254}
255
256static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = {
257 .transfer = tc358768_dsi_host_transfer,
258};
259
260static void tc358768_sw_reset(struct udevice *dev)
261{
262 /* Assert Reset */
263 tc358768_write(dev, TC358768_SYSCTL, 1);
264 mdelay(5);
265
266 /* Release Reset, Exit Sleep */
267 tc358768_write(dev, TC358768_SYSCTL, 0);
268}
269
Svyatoslav Ryhel73091cc2025-02-14 15:28:28 +0200270static void tc358768_hw_enable(struct udevice *dev)
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +0200271{
Svyatoslav Ryhel73091cc2025-02-14 15:28:28 +0200272 struct tc358768_priv *priv = dev_get_priv(dev);
273 struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +0200274 int ret;
275
276 ret = clk_prepare_enable(priv->refclk);
277 if (ret)
278 log_debug("%s: error enabling refclk (%d)\n", __func__, ret);
279
280 ret = regulator_set_enable_if_allowed(priv->vddc, true);
281 if (ret)
282 log_debug("%s: error enabling vddc (%d)\n", __func__, ret);
283
284 ret = regulator_set_enable_if_allowed(priv->vddmipi, true);
285 if (ret)
286 log_debug("%s: error enabling vddmipi (%d)\n", __func__, ret);
287
288 mdelay(10);
289
290 ret = regulator_set_enable_if_allowed(priv->vddio, true);
291 if (ret)
292 log_debug("%s: error enabling vddio (%d)\n", __func__, ret);
293
294 mdelay(2);
295
296 /*
297 * The RESX is active low (GPIO_ACTIVE_LOW).
298 * DEASSERT (value = 0) the reset_gpio to enable the chip
299 */
Svyatoslav Ryhel73091cc2025-02-14 15:28:28 +0200300 ret = dm_gpio_set_value(&uc_priv->reset, 0);
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +0200301 if (ret)
302 log_debug("%s: error changing reset-gpio (%d)\n", __func__, ret);
303
304 /* wait for encoder clocks to stabilize */
305 mdelay(2);
306}
307
308static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
309{
310 return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes);
311}
312
313static int tc358768_calc_pll(struct tc358768_priv *priv,
314 struct display_timing *dt)
315{
316 static const u32 frs_limits[] = {
317 1000000000,
318 500000000,
319 250000000,
320 125000000,
321 62500000
322 };
323 unsigned long refclk;
324 u32 prd, target_pll, i, max_pll, min_pll;
325 u32 frs, best_diff, best_pll, best_prd, best_fbd;
326
327 target_pll = tc358768_pclk_to_pll(priv, dt->pixelclock.typ);
328
329 /* pll_clk = RefClk * FBD / PRD * (1 / (2^FRS)) */
330
331 for (i = 0; i < ARRAY_SIZE(frs_limits); i++)
332 if (target_pll >= frs_limits[i])
333 break;
334
335 if (i == ARRAY_SIZE(frs_limits) || i == 0)
336 return -EINVAL;
337
338 frs = i - 1;
339 max_pll = frs_limits[i - 1];
340 min_pll = frs_limits[i];
341
342 refclk = clk_get_rate(priv->refclk);
343
344 best_diff = UINT_MAX;
345 best_pll = 0;
346 best_prd = 0;
347 best_fbd = 0;
348
349 for (prd = 1; prd <= 16; ++prd) {
350 u32 divisor = prd * (1 << frs);
351 u32 fbd;
352
353 for (fbd = 1; fbd <= 512; ++fbd) {
354 u32 pll, diff, pll_in;
355
356 pll = (u32)div_u64((u64)refclk * fbd, divisor);
357
358 if (pll >= max_pll || pll < min_pll)
359 continue;
360
361 pll_in = (u32)div_u64((u64)refclk, prd);
362 if (pll_in < 4000000)
363 continue;
364
365 diff = max(pll, target_pll) - min(pll, target_pll);
366
367 if (diff < best_diff) {
368 best_diff = diff;
369 best_pll = pll;
370 best_prd = prd;
371 best_fbd = fbd;
372
373 if (best_diff == 0)
374 goto found;
375 }
376 }
377 }
378
379 if (best_diff == UINT_MAX) {
380 log_debug("%s: could not find suitable PLL setup\n", __func__);
381 return -EINVAL;
382 }
383
384found:
385 priv->fbd = best_fbd;
386 priv->prd = best_prd;
387 priv->frs = frs;
388 priv->dsiclk = best_pll / 2;
389
390 return 0;
391}
392
393static void tc358768_setup_pll(struct udevice *dev)
394{
395 struct tc358768_priv *priv = dev_get_priv(dev);
396 u32 fbd, prd, frs;
397 int ret;
398
399 ret = tc358768_calc_pll(priv, &priv->timing);
400 if (ret)
401 log_debug("%s: PLL calculation failed: %d\n", __func__, ret);
402
403 fbd = priv->fbd;
404 prd = priv->prd;
405 frs = priv->frs;
406
407 log_debug("%s: PLL: refclk %lu, fbd %u, prd %u, frs %u\n", __func__,
408 clk_get_rate(priv->refclk), fbd, prd, frs);
409 log_debug("%s: PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n", __func__,
410 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);
411
412 /* PRD[15:12] FBD[8:0] */
413 tc358768_write(dev, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1));
414
415 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */
416 tc358768_write(dev, TC358768_PLLCTL1,
417 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
418
419 /* wait for lock */
420 mdelay(5);
421
422 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */
423 tc358768_write(dev, TC358768_PLLCTL1,
424 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));
425}
426
427static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps)
428{
429 return DIV_ROUND_UP(ns * 1000, period_ps);
430}
431
432static u32 tc358768_ps_to_ns(u32 ps)
433{
434 return ps / 1000;
435}
436
437static u32 tc358768_dpi_to_ns(u32 val, u32 pclk)
438{
439 return (u32)div_u64((u64)val * NANO, pclk);
440}
441
442/* Convert value in DPI pixel clock units to DSI byte count */
443static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val)
444{
445 u64 m = (u64)val * priv->dsiclk / 4 * priv->dsi_lanes;
446 u64 n = priv->timing.pixelclock.typ;
447
448 return (u32)div_u64(m + n - 1, n);
449}
450
451static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val)
452{
453 u64 m = (u64)val * NANO;
454 u64 n = priv->dsiclk / 4 * priv->dsi_lanes;
455
456 return (u32)div_u64(m, n);
457}
458
459static int tc358768_attach(struct udevice *dev)
460{
461 struct tc358768_priv *priv = dev_get_priv(dev);
462 struct mipi_dsi_device *device = &priv->device;
463 struct display_timing *dt = &priv->timing;
464 u32 val, val2, lptxcnt, hact, data_type;
465 s32 raw_val;
466 u32 hsbyteclk_ps, dsiclk_ps, ui_ps;
467 u32 dsiclk, hsbyteclk;
468 int i;
469 /* In pixelclock units */
470 u32 dpi_htot, dpi_data_start;
471 /* In byte units */
472 u32 dsi_dpi_htot, dsi_dpi_data_start;
473 u32 dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp;
474 const u32 dsi_hss = 4; /* HSS is a short packet (4 bytes) */
475 /* In hsbyteclk units */
476 u32 dsi_vsdly;
477 const u32 internal_dly = 40;
478
479 if (device->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
480 debug("%s: Non-continuous mode unimplemented, falling back to continuous\n", __func__);
481 device->mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
482 }
483
Svyatoslav Ryhel73091cc2025-02-14 15:28:28 +0200484 tc358768_hw_enable(dev);
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +0200485 tc358768_sw_reset(dev);
486
487 tc358768_setup_pll(dev);
488
489 dsiclk = priv->dsiclk;
490 hsbyteclk = dsiclk / 4;
491
492 /* Data Format Control Register */
493 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */
494 switch (device->format) {
495 case MIPI_DSI_FMT_RGB888:
496 val |= (0x3 << 4);
497 hact = dt->hactive.typ * 3;
498 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
499 break;
500 case MIPI_DSI_FMT_RGB666:
501 val |= (0x4 << 4);
502 hact = dt->hactive.typ * 3;
503 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
504 break;
505 case MIPI_DSI_FMT_RGB666_PACKED:
506 val |= (0x4 << 4) | BIT(3);
507 hact = dt->hactive.typ * 18 / 8;
508 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
509 break;
510 case MIPI_DSI_FMT_RGB565:
511 val |= (0x5 << 4);
512 hact = dt->hactive.typ * 2;
513 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
514 break;
515 default:
516 log_debug("%s: Invalid data format (%u)\n",
517 __func__, device->format);
518 return -EINVAL;
519 }
520
521 /*
522 * There are three important things to make TC358768 work correctly,
523 * which are not trivial to manage:
524 *
525 * 1. Keep the DPI line-time and the DSI line-time as close to each
526 * other as possible.
527 * 2. TC358768 goes to LP mode after each line's active area. The DSI
528 * HFP period has to be long enough for entering and exiting LP mode.
529 * But it is not clear how to calculate this.
530 * 3. VSDly (video start delay) has to be long enough to ensure that the
531 * DSI TX does not start transmitting until we have started receiving
532 * pixel data from the DPI input. It is not clear how to calculate
533 * this either.
534 */
535
536 dpi_htot = dt->hactive.typ + dt->hfront_porch.typ +
537 dt->hsync_len.typ + dt->hback_porch.typ;
538 dpi_data_start = dt->hsync_len.typ + dt->hback_porch.typ;
539
540 log_debug("%s: dpi horiz timing (pclk): %u + %u + %u + %u = %u\n", __func__,
541 dt->hsync_len.typ, dt->hback_porch.typ, dt->hactive.typ,
542 dt->hfront_porch.typ, dpi_htot);
543
544 log_debug("%s: dpi horiz timing (ns): %u + %u + %u + %u = %u\n", __func__,
545 tc358768_dpi_to_ns(dt->hsync_len.typ, dt->pixelclock.typ),
546 tc358768_dpi_to_ns(dt->hback_porch.typ, dt->pixelclock.typ),
547 tc358768_dpi_to_ns(dt->hactive.typ, dt->pixelclock.typ),
548 tc358768_dpi_to_ns(dt->hfront_porch.typ, dt->pixelclock.typ),
549 tc358768_dpi_to_ns(dpi_htot, dt->pixelclock.typ));
550
551 log_debug("%s: dpi data start (ns): %u + %u = %u\n", __func__,
552 tc358768_dpi_to_ns(dt->hsync_len.typ, dt->pixelclock.typ),
553 tc358768_dpi_to_ns(dt->hback_porch.typ, dt->pixelclock.typ),
554 tc358768_dpi_to_ns(dpi_data_start, dt->pixelclock.typ));
555
556 dsi_dpi_htot = tc358768_dpi_to_dsi_bytes(priv, dpi_htot);
557 dsi_dpi_data_start = tc358768_dpi_to_dsi_bytes(priv, dpi_data_start);
558
559 if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
560 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, dt->hsync_len.typ);
561 dsi_hbp = tc358768_dpi_to_dsi_bytes(priv, dt->hback_porch.typ);
562 } else {
563 /* HBP is included in HSW in event mode */
564 dsi_hbp = 0;
565 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv,
566 dt->hsync_len.typ +
567 dt->hback_porch.typ);
568
569 /*
570 * The pixel packet includes the actual pixel data, and:
571 * DSI packet header = 4 bytes
572 * DCS code = 1 byte
573 * DSI packet footer = 2 bytes
574 */
575 dsi_hact = hact + 4 + 1 + 2;
576
577 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss;
578
579 /*
580 * Here we should check if HFP is long enough for entering LP
581 * and exiting LP, but it's not clear how to calculate that.
582 * Instead, this is a naive algorithm that just adjusts the HFP
583 * and HSW so that HFP is (at least) roughly 2/3 of the total
584 * blanking time.
585 */
586 if (dsi_hfp < (dsi_hfp + dsi_hsw + dsi_hss) * 2 / 3) {
587 u32 old_hfp = dsi_hfp;
588 u32 old_hsw = dsi_hsw;
589 u32 tot = dsi_hfp + dsi_hsw + dsi_hss;
590
591 dsi_hsw = tot / 3;
592
593 /*
594 * Seems like sometimes HSW has to be divisible by num-lanes, but
595 * not always...
596 */
597 dsi_hsw = roundup(dsi_hsw, priv->dsi_lanes);
598
599 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss;
600
601 log_debug("%s: hfp too short, adjusting dsi hfp and dsi hsw from %u, %u to %u, %u\n",
602 __func__, old_hfp, old_hsw, dsi_hfp, dsi_hsw);
603 }
604
605 log_debug("%s: dsi horiz timing (bytes): %u, %u + %u + %u + %u = %u\n", __func__,
606 dsi_hss, dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp,
607 dsi_hss + dsi_hsw + dsi_hbp + dsi_hact + dsi_hfp);
608
609 log_debug("%s: dsi horiz timing (ns): %u + %u + %u + %u + %u = %u\n", __func__,
610 tc358768_dsi_bytes_to_ns(priv, dsi_hss),
611 tc358768_dsi_bytes_to_ns(priv, dsi_hsw),
612 tc358768_dsi_bytes_to_ns(priv, dsi_hbp),
613 tc358768_dsi_bytes_to_ns(priv, dsi_hact),
614 tc358768_dsi_bytes_to_ns(priv, dsi_hfp),
615 tc358768_dsi_bytes_to_ns(priv, dsi_hss + dsi_hsw +
616 dsi_hbp + dsi_hact + dsi_hfp));
617 }
618
619 /* VSDly calculation */
620
621 /* Start with the HW internal delay */
622 dsi_vsdly = internal_dly;
623
624 /* Convert to byte units as the other variables are in byte units */
625 dsi_vsdly *= priv->dsi_lanes;
626
627 /* Do we need more delay, in addition to the internal? */
628 if (dsi_dpi_data_start > dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp) {
629 dsi_vsdly = dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp;
630 dsi_vsdly = roundup(dsi_vsdly, priv->dsi_lanes);
631 }
632
633 log_debug("%s: dsi data start (bytes) %u + %u + %u + %u = %u\n", __func__,
634 dsi_vsdly, dsi_hss, dsi_hsw, dsi_hbp,
635 dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp);
636
637 log_debug("%s: dsi data start (ns) %u + %u + %u + %u = %u\n", __func__,
638 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly),
639 tc358768_dsi_bytes_to_ns(priv, dsi_hss),
640 tc358768_dsi_bytes_to_ns(priv, dsi_hsw),
641 tc358768_dsi_bytes_to_ns(priv, dsi_hbp),
642 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp));
643
644 /* Convert back to hsbyteclk */
645 dsi_vsdly /= priv->dsi_lanes;
646
647 /*
648 * The docs say that there is an internal delay of 40 cycles.
649 * However, we get underflows if we follow that rule. If we
650 * instead ignore the internal delay, things work. So either
651 * the docs are wrong or the calculations are wrong.
652 *
653 * As a temporary fix, add the internal delay here, to counter
654 * the subtraction when writing the register.
655 */
656 dsi_vsdly += internal_dly;
657
658 /* Clamp to the register max */
659 if (dsi_vsdly - internal_dly > 0x3ff) {
660 log_warning("%s: VSDly too high, underflows likely\n", __func__);
661 dsi_vsdly = 0x3ff + internal_dly;
662 }
663
664 /* VSDly[9:0] */
665 tc358768_write(dev, TC358768_VSDLY, dsi_vsdly - internal_dly);
666
667 tc358768_write(dev, TC358768_DATAFMT, val);
668 tc358768_write(dev, TC358768_DSITX_DT, data_type);
669
670 /* Enable D-PHY (HiZ->LP11) */
671 tc358768_write(dev, TC358768_CLW_CNTRL, 0x0000);
672 /* Enable lanes */
673 for (i = 0; i < device->lanes; i++)
674 tc358768_write(dev, TC358768_D0W_CNTRL + i * 4, 0x0000);
675
676 /* Set up D-PHY CONTTX */
677 tc358768_write(dev, TC358768_CLW_DPHYCONTTX, 0x0203);
678 /* Adjust lanes */
679 for (i = 0; i < device->lanes; i++)
680 tc358768_write(dev, TC358768_D0W_DPHYCONTTX + i * 4, 0x0203);
681
682 /* DSI Timings */
683 hsbyteclk_ps = (u32)div_u64(PICO, hsbyteclk);
684 dsiclk_ps = (u32)div_u64(PICO, dsiclk);
685 ui_ps = dsiclk_ps / 2;
686 log_debug("%s: dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n",
687 __func__, dsiclk_ps, ui_ps, hsbyteclk_ps);
688
689 /* LP11 > 100us for D-PHY Rx Init */
690 val = tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1;
691 log_debug("%s: LINEINITCNT: 0x%x\n", __func__, val);
692 tc358768_write(dev, TC358768_LINEINITCNT, val);
693
694 /* LPTimeCnt > 50ns */
695 val = tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1;
696 lptxcnt = val;
697 log_debug("%s: LPTXTIMECNT: 0x%x\n", __func__, val);
698 tc358768_write(dev, TC358768_LPTXTIMECNT, val);
699
700 /* 38ns < TCLK_PREPARE < 95ns */
701 val = tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1;
702 log_debug("%s: TCLK_PREPARECNT: 0x%x\n", __func__, val);
703 /* TCLK_PREPARE + TCLK_ZERO > 300ns */
704 val2 = tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps),
705 hsbyteclk_ps) - 2;
706 log_debug("%s: TCLK_ZEROCNT: 0x%x\n", __func__, val2);
707 val |= val2 << 8;
708 tc358768_write(dev, TC358768_TCLK_HEADERCNT, val);
709
710 /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */
711 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps),
712 hsbyteclk_ps) - 5;
713 val = clamp(raw_val, 0, 127);
714 log_debug("%s: TCLK_TRAILCNT: 0x%x\n", __func__, val);
715 tc358768_write(dev, TC358768_TCLK_TRAILCNT, val);
716
717 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
718 val = 50 + tc358768_ps_to_ns(4 * ui_ps);
719 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1;
720 log_debug("%s: THS_PREPARECNT: 0x%x\n", __func__, val);
721 /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */
722 raw_val = tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps),
723 hsbyteclk_ps) - 10;
724 val2 = clamp(raw_val, 0, 127);
725 log_debug("%s: THS_ZEROCNT: 0x%x\n", __func__, val2);
726 val |= val2 << 8;
727 tc358768_write(dev, TC358768_THS_HEADERCNT, val);
728
729 /* TWAKEUP > 1ms in lptxcnt steps */
730 val = tc358768_ns_to_cnt(1020000, hsbyteclk_ps);
731 val = val / (lptxcnt + 1) - 1;
732 log_debug("%s: TWAKEUP: 0x%x\n", __func__, val);
733 tc358768_write(dev, TC358768_TWAKEUP, val);
734
735 /* TCLK_POSTCNT > 60ns + 52*UI */
736 val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps),
737 hsbyteclk_ps) - 3;
738 log_debug("%s: TCLK_POSTCNT: 0x%x\n", __func__, val);
739 tc358768_write(dev, TC358768_TCLK_POSTCNT, val);
740
741 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */
742 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps),
743 hsbyteclk_ps) - 4;
744 val = clamp(raw_val, 0, 15);
745 log_debug("%s: THS_TRAILCNT: 0x%x\n", __func__, val);
746 tc358768_write(dev, TC358768_THS_TRAILCNT, val);
747
748 val = BIT(0);
749 for (i = 0; i < device->lanes; i++)
750 val |= BIT(i + 1);
751 tc358768_write(dev, TC358768_HSTXVREGEN, val);
752
753 tc358768_write(dev, TC358768_TXOPTIONCNTRL,
754 (device->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0));
755
756 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
757 val = tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4);
758 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1;
759 log_debug("%s: TXTAGOCNT: 0x%x\n", __func__, val);
760 val2 = tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps),
761 hsbyteclk_ps) - 2;
762 log_debug("%s: RXTASURECNT: 0x%x\n", __func__, val2);
763 val = val << 16 | val2;
764 tc358768_write(dev, TC358768_BTACNTRL1, val);
765
766 /* START[0] */
767 tc358768_write(dev, TC358768_STARTCNTRL, 1);
768
769 if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
770 /* Set pulse mode */
771 tc358768_write(dev, TC358768_DSI_EVENT, 0);
772
773 /* vact */
774 tc358768_write(dev, TC358768_DSI_VACT, dt->vactive.typ);
775 /* vsw */
776 tc358768_write(dev, TC358768_DSI_VSW, dt->vsync_len.typ);
777 /* vbp */
778 tc358768_write(dev, TC358768_DSI_VBPR, dt->vback_porch.typ);
779 } else {
780 /* Set event mode */
781 tc358768_write(dev, TC358768_DSI_EVENT, 1);
782
783 /* vact */
784 tc358768_write(dev, TC358768_DSI_VACT, dt->vactive.typ);
785
786 /* vsw (+ vbp) */
787 tc358768_write(dev, TC358768_DSI_VSW,
788 dt->vsync_len.typ + dt->vback_porch.typ);
789 /* vbp (not used in event mode) */
790 tc358768_write(dev, TC358768_DSI_VBPR, 0);
791 }
792
793 /* hsw (bytes) */
794 tc358768_write(dev, TC358768_DSI_HSW, dsi_hsw);
795
796 /* hbp (bytes) */
797 tc358768_write(dev, TC358768_DSI_HBPR, dsi_hbp);
798
799 /* hact (bytes) */
800 tc358768_write(dev, TC358768_DSI_HACT, hact);
801
802 /* VSYNC polarity */
803 tc358768_update_bits(dev, TC358768_CONFCTL, BIT(5),
804 (dt->flags & DISPLAY_FLAGS_VSYNC_HIGH) ? BIT(5) : 0);
805
806 /* HSYNC polarity */
807 tc358768_update_bits(dev, TC358768_PP_MISC, BIT(0),
808 (dt->flags & DISPLAY_FLAGS_HSYNC_LOW) ? BIT(0) : 0);
809
810 /* Start DSI Tx */
811 tc358768_write(dev, TC358768_DSI_START, 0x1);
812
813 /* Configure DSI_Control register */
814 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
815 val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD |
816 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS;
817 tc358768_write(dev, TC358768_DSI_CONFW, val);
818
819 val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
820 val |= (device->lanes - 1) << 1;
821
822 val |= TC358768_DSI_CONTROL_TXMD;
823
824 if (!(device->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
825 val |= TC358768_DSI_CONTROL_HSCKMD;
826
827 /*
828 * TODO: Actually MIPI_DSI_MODE_NO_EOT_PACKET
829 *
830 * Many of the DSI flags have names opposite to their
831 * actual effects, e.g. MIPI_DSI_MODE_EOT_PACKET means
832 * that EoT packets will actually be disabled.
833 */
834 if (device->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
835 val |= TC358768_DSI_CONTROL_EOTDIS;
836
837 tc358768_write(dev, TC358768_DSI_CONFW, val);
838
839 val = TC358768_DSI_CONFW_MODE_CLR |
840 TC358768_DSI_CONFW_ADDR_DSI_CONTROL |
841 TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */
842 tc358768_write(dev, TC358768_DSI_CONFW, val);
843
844 /* clear FrmStop and RstPtr */
845 tc358768_update_bits(dev, TC358768_PP_MISC, 0x3 << 14, 0);
846
847 /* set PP_en */
848 tc358768_update_bits(dev, TC358768_CONFCTL, BIT(6), BIT(6));
849
850 /* Set up panel configuration */
851 return panel_enable_backlight(priv->panel);
852}
853
854static int tc358768_set_backlight(struct udevice *dev, int percent)
855{
856 struct tc358768_priv *priv = dev_get_priv(dev);
857
858 return panel_set_backlight(priv->panel, percent);
859}
860
861static int tc358768_panel_timings(struct udevice *dev,
862 struct display_timing *timing)
863{
864 struct tc358768_priv *priv = dev_get_priv(dev);
865
866 /* Default to positive sync */
867
868 if (!(priv->timing.flags &
869 (DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_HSYNC_HIGH)))
870 priv->timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
871
872 if (!(priv->timing.flags &
873 (DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH)))
874 priv->timing.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
875
876 memcpy(timing, &priv->timing, sizeof(*timing));
877
878 return 0;
879}
880
Svyatoslav Ryhela7ae9882025-02-21 13:29:43 +0200881static int tc358768_get_panel(struct udevice *dev)
882{
883 struct tc358768_priv *priv = dev_get_priv(dev);
884 int i, ret;
885
886 u32 num = ofnode_graph_get_port_count(dev_ofnode(dev));
887
888 for (i = 0; i < num; i++) {
889 ofnode remote = ofnode_graph_get_remote_node(dev_ofnode(dev), i, -1);
890
891 ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote,
892 &priv->panel);
893 if (!ret)
894 return 0;
895 }
896
897 /* If this point is reached, no panels were found */
898 return -ENODEV;
899}
900
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +0200901static int tc358768_setup(struct udevice *dev)
902{
903 struct tc358768_priv *priv = dev_get_priv(dev);
Svyatoslav Ryhel73091cc2025-02-14 15:28:28 +0200904 struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +0200905 struct mipi_dsi_device *device = &priv->device;
906 struct mipi_dsi_panel_plat *mipi_plat;
907 int ret;
908
909 /* The bridge uses 16 bit registers */
910 ret = i2c_set_chip_offset_len(dev, 2);
911 if (ret) {
912 log_debug("%s: set_chip_offset_len failed: %d\n",
913 __func__, ret);
914 return ret;
915 }
916
Svyatoslav Ryhela7ae9882025-02-21 13:29:43 +0200917 ret = tc358768_get_panel(dev);
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +0200918 if (ret) {
Svyatoslav Ryhela7ae9882025-02-21 13:29:43 +0200919 log_debug("%s: panel not found, ret %d\n", __func__, ret);
920 return ret;
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +0200921 }
922
923 panel_get_display_timing(priv->panel, &priv->timing);
924
925 mipi_plat = dev_get_plat(priv->panel);
926 mipi_plat->device = device;
927
928 priv->host.dev = (struct device *)dev;
929 priv->host.ops = &tc358768_dsi_host_ops;
930
931 device->host = &priv->host;
932 device->lanes = mipi_plat->lanes;
933 device->format = mipi_plat->format;
934 device->mode_flags = mipi_plat->mode_flags;
935
936 priv->pd_lines = mipi_dsi_pixel_format_to_bpp(device->format);
937 priv->dsi_lanes = device->lanes;
938
939 /* get regulators */
940 ret = device_get_supply_regulator(dev, "vddc-supply", &priv->vddc);
941 if (ret) {
942 log_debug("%s: vddc regulator error: %d\n", __func__, ret);
943 if (ret != -ENOENT)
944 return log_ret(ret);
945 }
946
947 ret = device_get_supply_regulator(dev, "vddmipi-supply", &priv->vddmipi);
948 if (ret) {
949 log_debug("%s: vddmipi regulator error: %d\n", __func__, ret);
950 if (ret != -ENOENT)
951 return log_ret(ret);
952 }
953
954 ret = device_get_supply_regulator(dev, "vddio-supply", &priv->vddio);
955 if (ret) {
956 log_debug("%s: vddio regulator error: %d\n", __func__, ret);
957 if (ret != -ENOENT)
958 return log_ret(ret);
959 }
960
961 /* get clk */
962 priv->refclk = devm_clk_get(dev, "refclk");
963 if (IS_ERR(priv->refclk)) {
964 log_debug("%s: Could not get refclk: %ld\n",
965 __func__, PTR_ERR(priv->refclk));
966 return PTR_ERR(priv->refclk);
967 }
968
Svyatoslav Ryhel73091cc2025-02-14 15:28:28 +0200969 dm_gpio_set_value(&uc_priv->reset, 1);
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +0200970
971 return 0;
972}
973
974static int tc358768_probe(struct udevice *dev)
975{
976 if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
977 return -EPROTONOSUPPORT;
978
979 return tc358768_setup(dev);
980}
981
Svyatoslav Ryhel73091cc2025-02-14 15:28:28 +0200982static const struct video_bridge_ops tc358768_ops = {
983 .attach = tc358768_attach,
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +0200984 .set_backlight = tc358768_set_backlight,
985 .get_display_timing = tc358768_panel_timings,
986};
987
988static const struct udevice_id tc358768_ids[] = {
989 { .compatible = "toshiba,tc358768" },
990 { .compatible = "toshiba,tc358778" },
991 { }
992};
993
994U_BOOT_DRIVER(tc358768) = {
995 .name = "tc358768",
Svyatoslav Ryhel73091cc2025-02-14 15:28:28 +0200996 .id = UCLASS_VIDEO_BRIDGE,
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +0200997 .of_match = tc358768_ids,
998 .ops = &tc358768_ops,
Svyatoslav Ryhela7ae9882025-02-21 13:29:43 +0200999 .bind = dm_scan_fdt_dev,
Svyatoslav Ryhelef1e26b2024-01-31 08:57:17 +02001000 .probe = tc358768_probe,
1001 .priv_auto = sizeof(struct tc358768_priv),
1002};