Blame - arch/blackfin/include/asm/mach-bf538/BF538_def.h - filogic/uboot

Mike Frysinger

5662611

2008-08-07 13:10:41 -0400

[diff] [blame]

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/* DO NOT EDIT THIS FILE

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* Automatically generated by generate-def-headers.xsl

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* DO NOT EDIT THIS FILE

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*/

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#ifndef __BFIN_DEF_ADSP_BF538_proc__

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#define __BFIN_DEF_ADSP_BF538_proc__

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#include "../mach-common/ADSP-EDN-core_def.h"

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#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */

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#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */

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#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */

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#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */

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#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */

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#define CHIPID 0xFFC00014

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#define SWRST 0xFFC00100 /* Software Reset Register */

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#define SYSCR 0xFFC00104 /* System Configuration register */

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#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */

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#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register 0 */

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#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */

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#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register 0 */

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#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */

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#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register 0 */

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#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */

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#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */

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#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */

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#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */

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#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */

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#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */

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#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */

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#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */

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#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */

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#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */

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#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */

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#define RTC_STAT 0xFFC00300

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#define RTC_ICTL 0xFFC00304

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#define RTC_ISTAT 0xFFC00308

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#define RTC_SWCNT 0xFFC0030C

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#define RTC_ALARM 0xFFC00310

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#define RTC_PREN 0xFFC00314

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#define UART0_THR 0xFFC00400

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#define UART0_RBR 0xFFC00400

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#define UART0_DLL 0xFFC00400

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#define UART0_DLH 0xFFC00404

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#define UART0_IER 0xFFC00404

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#define UART0_IIR 0xFFC00408

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#define UART0_LCR 0xFFC0040C

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#define UART0_MCR 0xFFC00410

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#define UART0_LSR 0xFFC00414

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#define UART0_SCR 0xFFC0041C

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#define UART0_GCTL 0xFFC00424

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#define UART1_THR 0xFFC02000

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#define UART1_RBR 0xFFC02000

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#define UART1_DLL 0xFFC02000

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#define UART1_DLH 0xFFC02004

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#define UART1_IER 0xFFC02004

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#define UART1_IIR 0xFFC02008

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#define UART1_LCR 0xFFC0200C

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#define UART1_MCR 0xFFC02010

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#define UART1_LSR 0xFFC02014

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#define UART1_SCR 0xFFC0201C

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#define UART1_GCTL 0xFFC02024

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#define UART2_THR 0xFFC02100

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#define UART2_RBR 0xFFC02100

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#define UART2_DLL 0xFFC02100

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#define UART2_DLH 0xFFC02104

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#define UART2_IER 0xFFC02104

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#define UART2_IIR 0xFFC02108

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#define UART2_LCR 0xFFC0210C

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#define UART2_MCR 0xFFC02110

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#define UART2_LSR 0xFFC02114

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#define UART2_SCR 0xFFC0211C

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#define UART2_GCTL 0xFFC02124

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#define SPI0_CTL 0xFFC00500

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#define SPI0_FLG 0xFFC00504

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#define SPI0_STAT 0xFFC00508

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#define SPI0_TDBR 0xFFC0050C

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#define SPI0_RDBR 0xFFC00510

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#define SPI0_BAUD 0xFFC00514

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#define SPI0_SHADOW 0xFFC00518

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#define SPI1_CTL 0xFFC02300

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#define SPI1_FLG 0xFFC02304

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#define SPI1_STAT 0xFFC02308

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#define SPI1_TDBR 0xFFC0230C

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#define SPI1_RDBR 0xFFC02310

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#define SPI1_BAUD 0xFFC02314

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#define SPI1_SHADOW 0xFFC02318

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#define SPI2_CTL 0xFFC02400

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#define SPI2_FLG 0xFFC02404

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#define SPI2_STAT 0xFFC02408

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#define SPI2_TDBR 0xFFC0240C

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#define SPI2_RDBR 0xFFC02410

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#define SPI2_BAUD 0xFFC02414

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#define SPI2_SHADOW 0xFFC02418

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#define TIMER0_CONFIG 0xFFC00600

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#define TIMER0_COUNTER 0xFFC00604

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#define TIMER0_PERIOD 0xFFC00608

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#define TIMER0_WIDTH 0xFFC0060C

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#define TIMER1_CONFIG 0xFFC00610

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#define TIMER1_COUNTER 0xFFC00614

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#define TIMER1_PERIOD 0xFFC00618

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#define TIMER1_WIDTH 0xFFC0061C

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#define TIMER2_CONFIG 0xFFC00620

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#define TIMER2_COUNTER 0xFFC00624

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#define TIMER2_PERIOD 0xFFC00628

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#define TIMER2_WIDTH 0xFFC0062C

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#define TIMER_ENABLE 0xFFC00640

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#define TIMER_DISABLE 0xFFC00644

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#define TIMER_STATUS 0xFFC00648

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#define SPORT0_TCR1 0xFFC00800

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#define SPORT0_TCR2 0xFFC00804

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#define SPORT0_TCLKDIV 0xFFC00808

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#define SPORT0_TFSDIV 0xFFC0080C

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#define SPORT0_TX 0xFFC00810

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#define SPORT0_RX 0xFFC00818

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#define SPORT0_RCR1 0xFFC00820

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#define SPORT0_RCR2 0xFFC00824

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#define SPORT0_RCLKDIV 0xFFC00828

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#define SPORT0_RFSDIV 0xFFC0082C

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#define SPORT0_STAT 0xFFC00830

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#define SPORT0_CHNL 0xFFC00834

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#define SPORT0_MCMC1 0xFFC00838

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#define SPORT0_MCMC2 0xFFC0083C

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#define SPORT0_MTCS0 0xFFC00840

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#define SPORT0_MTCS1 0xFFC00844

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#define SPORT0_MTCS2 0xFFC00848

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#define SPORT0_MTCS3 0xFFC0084C

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#define SPORT0_MRCS0 0xFFC00850

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#define SPORT0_MRCS1 0xFFC00854

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#define SPORT0_MRCS2 0xFFC00858

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#define SPORT0_MRCS3 0xFFC0085C

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#define SPORT1_TCR1 0xFFC00900

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#define SPORT1_TCR2 0xFFC00904

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#define SPORT1_TCLKDIV 0xFFC00908

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#define SPORT1_TFSDIV 0xFFC0090C

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#define SPORT1_TX 0xFFC00910

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#define SPORT1_RX 0xFFC00918

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#define SPORT1_RCR1 0xFFC00920

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#define SPORT1_RCR2 0xFFC00924

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#define SPORT1_RCLKDIV 0xFFC00928

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#define SPORT1_RFSDIV 0xFFC0092C

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#define SPORT1_STAT 0xFFC00930

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#define SPORT1_CHNL 0xFFC00934

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#define SPORT1_MCMC1 0xFFC00938

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#define SPORT1_MCMC2 0xFFC0093C

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#define SPORT1_MTCS0 0xFFC00940

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#define SPORT1_MTCS1 0xFFC00944

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#define SPORT1_MTCS2 0xFFC00948

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#define SPORT1_MTCS3 0xFFC0094C

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#define SPORT1_MRCS0 0xFFC00950

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#define SPORT1_MRCS1 0xFFC00954

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#define SPORT1_MRCS2 0xFFC00958

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#define SPORT1_MRCS3 0xFFC0095C

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#define SPORT2_TCR1 0xFFC02500

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#define SPORT2_TCR2 0xFFC02504

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#define SPORT2_TCLKDIV 0xFFC02508

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#define SPORT2_TFSDIV 0xFFC0250C

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#define SPORT2_TX 0xFFC02510

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#define SPORT2_RX 0xFFC02518

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#define SPORT2_RCR1 0xFFC02520

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#define SPORT2_RCR2 0xFFC02524

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#define SPORT2_RCLKDIV 0xFFC02528

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#define SPORT2_RFSDIV 0xFFC0252C

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#define SPORT2_STAT 0xFFC02530

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#define SPORT2_CHNL 0xFFC02534

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#define SPORT2_MCMC1 0xFFC02538

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#define SPORT2_MCMC2 0xFFC0253C

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#define SPORT2_MTCS0 0xFFC02540

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#define SPORT2_MTCS1 0xFFC02544

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#define SPORT2_MTCS2 0xFFC02548

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#define SPORT2_MTCS3 0xFFC0254C

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#define SPORT2_MRCS0 0xFFC02550

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#define SPORT2_MRCS1 0xFFC02554

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#define SPORT2_MRCS2 0xFFC02558

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#define SPORT2_MRCS3 0xFFC0255C

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#define SPORT3_TCR1 0xFFC02600

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#define SPORT3_TCR2 0xFFC02604

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#define SPORT3_TCLKDIV 0xFFC02608

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#define SPORT3_TFSDIV 0xFFC0260C

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#define SPORT3_TX 0xFFC02610

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#define SPORT3_RX 0xFFC02618

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#define SPORT3_RCR1 0xFFC02620

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#define SPORT3_RCR2 0xFFC02624

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#define SPORT3_RCLKDIV 0xFFC02628

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#define SPORT3_RFSDIV 0xFFC0262C

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#define SPORT3_STAT 0xFFC02630

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#define SPORT3_CHNL 0xFFC02634

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#define SPORT3_MCMC1 0xFFC02638

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#define SPORT3_MCMC2 0xFFC0263C

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#define SPORT3_MTCS0 0xFFC02640

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#define SPORT3_MTCS1 0xFFC02644

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#define SPORT3_MTCS2 0xFFC02648

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#define SPORT3_MTCS3 0xFFC0264C

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#define SPORT3_MRCS0 0xFFC02650

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#define SPORT3_MRCS1 0xFFC02654

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#define SPORT3_MRCS2 0xFFC02658

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#define SPORT3_MRCS3 0xFFC0265C

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#define PORTFIO 0xFFC00700

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#define PORTFIO_CLEAR 0xFFC00704

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#define PORTFIO_SET 0xFFC00708

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#define PORTFIO_TOGGLE 0xFFC0070C

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#define PORTFIO_MASKA 0xFFC00710

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#define PORTFIO_MASKA_CLEAR 0xFFC00714

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#define PORTFIO_MASKA_SET 0xFFC00718

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#define PORTFIO_MASKA_TOGGLE 0xFFC0071C

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#define PORTFIO_MASKB 0xFFC00720

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#define PORTFIO_MASKB_CLEAR 0xFFC00724

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#define PORTFIO_MASKB_SET 0xFFC00728

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#define PORTFIO_MASKB_TOGGLE 0xFFC0072C

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#define PORTFIO_DIR 0xFFC00730

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#define PORTFIO_POLAR 0xFFC00734

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#define PORTFIO_EDGE 0xFFC00738

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#define PORTFIO_BOTH 0xFFC0073C

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#define PORTFIO_INEN 0xFFC00740

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#define PORTCIO_FER 0xFFC01500

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#define PORTCIO 0xFFC01510

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#define PORTCIO_CLEAR 0xFFC01520

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#define PORTCIO_SET 0xFFC01530

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#define PORTCIO_TOGGLE 0xFFC01540

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#define PORTCIO_DIR 0xFFC01550

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#define PORTCIO_INEN 0xFFC01560

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#define PORTDIO_FER 0xFFC01504

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#define PORTDIO 0xFFC01514

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#define PORTDIO_CLEAR 0xFFC01524

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#define PORTDIO_SET 0xFFC01534

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#define PORTDIO_TOGGLE 0xFFC01544

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#define PORTDIO_DIR 0xFFC01554

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#define PORTDIO_INEN 0xFFC01564

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#define PORTEIO_FER 0xFFC01508

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#define PORTEIO 0xFFC01518

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#define PORTEIO_CLEAR 0xFFC01528

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#define PORTEIO_SET 0xFFC01538

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#define PORTEIO_TOGGLE 0xFFC01548

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#define PORTEIO_DIR 0xFFC01558

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#define PORTEIO_INEN 0xFFC01568

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#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */

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#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */

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#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */

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#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */

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#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */

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#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */

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#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */

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#define DMA0_TC_PER 0xFFC00B0C /* Traffic Control Periods */

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#define DMA0_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts */

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#define DMA0_NEXT_DESC_PTR 0xFFC00C00

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#define DMA0_START_ADDR 0xFFC00C04

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#define DMA0_CONFIG 0xFFC00C08

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#define DMA0_X_COUNT 0xFFC00C10

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#define DMA0_X_MODIFY 0xFFC00C14

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#define DMA0_Y_COUNT 0xFFC00C18

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#define DMA0_Y_MODIFY 0xFFC00C1C

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#define DMA0_CURR_DESC_PTR 0xFFC00C20

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#define DMA0_CURR_ADDR 0xFFC00C24

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#define DMA0_IRQ_STATUS 0xFFC00C28

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#define DMA0_PERIPHERAL_MAP 0xFFC00C2C

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#define DMA0_CURR_X_COUNT 0xFFC00C30

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#define DMA0_CURR_Y_COUNT 0xFFC00C38

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#define DMA1_NEXT_DESC_PTR 0xFFC00C40

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#define DMA1_START_ADDR 0xFFC00C44

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#define DMA1_CONFIG 0xFFC00C48

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#define DMA1_X_COUNT 0xFFC00C50

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#define DMA1_X_MODIFY 0xFFC00C54

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#define DMA1_Y_COUNT 0xFFC00C58

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#define DMA1_Y_MODIFY 0xFFC00C5C

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#define DMA1_CURR_DESC_PTR 0xFFC00C60

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#define DMA1_CURR_ADDR 0xFFC00C64

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#define DMA1_IRQ_STATUS 0xFFC00C68

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#define DMA1_PERIPHERAL_MAP 0xFFC00C6C

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#define DMA1_CURR_X_COUNT 0xFFC00C70

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#define DMA1_CURR_Y_COUNT 0xFFC00C78

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#define DMA2_NEXT_DESC_PTR 0xFFC00C80

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#define DMA2_START_ADDR 0xFFC00C84

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#define DMA2_CONFIG 0xFFC00C88

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#define DMA2_X_COUNT 0xFFC00C90

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#define DMA2_X_MODIFY 0xFFC00C94

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#define DMA2_Y_COUNT 0xFFC00C98

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#define DMA2_Y_MODIFY 0xFFC00C9C

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#define DMA2_CURR_DESC_PTR 0xFFC00CA0

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#define DMA2_CURR_ADDR 0xFFC00CA4

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#define DMA2_IRQ_STATUS 0xFFC00CA8

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#define DMA2_PERIPHERAL_MAP 0xFFC00CAC

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#define DMA2_CURR_X_COUNT 0xFFC00CB0

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#define DMA2_CURR_Y_COUNT 0xFFC00CB8

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#define DMA3_NEXT_DESC_PTR 0xFFC00CC0

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#define DMA3_START_ADDR 0xFFC00CC4

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#define DMA3_CONFIG 0xFFC00CC8

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#define DMA3_X_COUNT 0xFFC00CD0

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#define DMA3_X_MODIFY 0xFFC00CD4

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#define DMA3_Y_COUNT 0xFFC00CD8

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#define DMA3_Y_MODIFY 0xFFC00CDC

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#define DMA3_CURR_DESC_PTR 0xFFC00CE0

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#define DMA3_CURR_ADDR 0xFFC00CE4

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#define DMA3_IRQ_STATUS 0xFFC00CE8

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#define DMA3_PERIPHERAL_MAP 0xFFC00CEC

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#define DMA3_CURR_X_COUNT 0xFFC00CF0

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#define DMA3_CURR_Y_COUNT 0xFFC00CF8

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#define DMA4_NEXT_DESC_PTR 0xFFC00D00

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#define DMA4_START_ADDR 0xFFC00D04

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#define DMA4_CONFIG 0xFFC00D08

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#define DMA4_X_COUNT 0xFFC00D10

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#define DMA4_X_MODIFY 0xFFC00D14

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#define DMA4_Y_COUNT 0xFFC00D18

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#define DMA4_Y_MODIFY 0xFFC00D1C

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#define DMA4_CURR_DESC_PTR 0xFFC00D20

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#define DMA4_CURR_ADDR 0xFFC00D24

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#define DMA4_IRQ_STATUS 0xFFC00D28

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#define DMA4_PERIPHERAL_MAP 0xFFC00D2C

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#define DMA4_CURR_X_COUNT 0xFFC00D30

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#define DMA4_CURR_Y_COUNT 0xFFC00D38

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#define DMA5_NEXT_DESC_PTR 0xFFC00D40

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#define DMA5_START_ADDR 0xFFC00D44

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#define DMA5_CONFIG 0xFFC00D48

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#define DMA5_X_COUNT 0xFFC00D50

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#define DMA5_X_MODIFY 0xFFC00D54

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#define DMA5_Y_COUNT 0xFFC00D58

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#define DMA5_Y_MODIFY 0xFFC00D5C

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#define DMA5_CURR_DESC_PTR 0xFFC00D60

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#define DMA5_CURR_ADDR 0xFFC00D64

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#define DMA5_IRQ_STATUS 0xFFC00D68

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#define DMA5_PERIPHERAL_MAP 0xFFC00D6C

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#define DMA5_CURR_X_COUNT 0xFFC00D70

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#define DMA5_CURR_Y_COUNT 0xFFC00D78

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#define DMA6_NEXT_DESC_PTR 0xFFC00D80

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#define DMA6_START_ADDR 0xFFC00D84

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#define DMA6_CONFIG 0xFFC00D88

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#define DMA6_X_COUNT 0xFFC00D90

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#define DMA6_X_MODIFY 0xFFC00D94

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#define DMA6_Y_COUNT 0xFFC00D98

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#define DMA6_Y_MODIFY 0xFFC00D9C

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#define DMA6_CURR_DESC_PTR 0xFFC00DA0

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#define DMA6_CURR_ADDR 0xFFC00DA4

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#define DMA6_IRQ_STATUS 0xFFC00DA8

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#define DMA6_PERIPHERAL_MAP 0xFFC00DAC

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#define DMA6_CURR_X_COUNT 0xFFC00DB0

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#define DMA6_CURR_Y_COUNT 0xFFC00DB8

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#define DMA7_NEXT_DESC_PTR 0xFFC00DC0

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#define DMA7_START_ADDR 0xFFC00DC4

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#define DMA7_CONFIG 0xFFC00DC8

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#define DMA7_X_COUNT 0xFFC00DD0

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#define DMA7_X_MODIFY 0xFFC00DD4

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#define DMA7_Y_COUNT 0xFFC00DD8

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#define DMA7_Y_MODIFY 0xFFC00DDC

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#define DMA7_CURR_DESC_PTR 0xFFC00DE0

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#define DMA7_CURR_ADDR 0xFFC00DE4

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#define DMA7_IRQ_STATUS 0xFFC00DE8

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#define DMA7_PERIPHERAL_MAP 0xFFC00DEC

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#define DMA7_CURR_X_COUNT 0xFFC00DF0

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#define DMA7_CURR_Y_COUNT 0xFFC00DF8

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#define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */

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#define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */

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#define DMA8_NEXT_DESC_PTR 0xFFC01C00

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#define DMA8_START_ADDR 0xFFC01C04

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#define DMA8_CONFIG 0xFFC01C08

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#define DMA8_X_COUNT 0xFFC01C10

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#define DMA8_X_MODIFY 0xFFC01C14

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#define DMA8_Y_COUNT 0xFFC01C18

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#define DMA8_Y_MODIFY 0xFFC01C1C

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#define DMA8_CURR_DESC_PTR 0xFFC01C20

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#define DMA8_CURR_ADDR 0xFFC01C24

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#define DMA8_IRQ_STATUS 0xFFC01C28

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#define DMA8_PERIPHERAL_MAP 0xFFC01C2C

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#define DMA8_CURR_X_COUNT 0xFFC01C30

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#define DMA8_CURR_Y_COUNT 0xFFC01C38

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#define DMA9_NEXT_DESC_PTR 0xFFC01C40

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#define DMA9_START_ADDR 0xFFC01C44

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#define DMA9_CONFIG 0xFFC01C48

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#define DMA9_X_COUNT 0xFFC01C50

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#define DMA9_X_MODIFY 0xFFC01C54

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#define DMA9_Y_COUNT 0xFFC01C58

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#define DMA9_Y_MODIFY 0xFFC01C5C

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#define DMA9_CURR_DESC_PTR 0xFFC01C60

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#define DMA9_CURR_ADDR 0xFFC01C64

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#define DMA9_IRQ_STATUS 0xFFC01C68

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#define DMA9_PERIPHERAL_MAP 0xFFC01C6C

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#define DMA9_CURR_X_COUNT 0xFFC01C70

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#define DMA9_CURR_Y_COUNT 0xFFC01C78

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#define DMA10_NEXT_DESC_PTR 0xFFC01C80

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#define DMA10_START_ADDR 0xFFC01C84

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#define DMA10_CONFIG 0xFFC01C88

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#define DMA10_X_COUNT 0xFFC01C90

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#define DMA10_X_MODIFY 0xFFC01C94

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#define DMA10_Y_COUNT 0xFFC01C98

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#define DMA10_Y_MODIFY 0xFFC01C9C

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#define DMA10_CURR_DESC_PTR 0xFFC01CA0

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#define DMA10_CURR_ADDR 0xFFC01CA4

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#define DMA10_IRQ_STATUS 0xFFC01CA8

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#define DMA10_PERIPHERAL_MAP 0xFFC01CAC

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#define DMA10_CURR_X_COUNT 0xFFC01CB0

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#define DMA10_CURR_Y_COUNT 0xFFC01CB8

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#define DMA11_NEXT_DESC_PTR 0xFFC01CC0

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#define DMA11_START_ADDR 0xFFC01CC4

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#define DMA11_CONFIG 0xFFC01CC8

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#define DMA11_X_COUNT 0xFFC01CD0

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#define DMA11_X_MODIFY 0xFFC01CD4

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#define DMA11_Y_COUNT 0xFFC01CD8

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#define DMA11_Y_MODIFY 0xFFC01CDC

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#define DMA11_CURR_DESC_PTR 0xFFC01CE0

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#define DMA11_CURR_ADDR 0xFFC01CE4

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#define DMA11_IRQ_STATUS 0xFFC01CE8

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#define DMA11_PERIPHERAL_MAP 0xFFC01CEC

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#define DMA11_CURR_X_COUNT 0xFFC01CF0

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#define DMA11_CURR_Y_COUNT 0xFFC01CF8

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#define DMA12_NEXT_DESC_PTR 0xFFC01D00

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#define DMA12_START_ADDR 0xFFC01D04

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#define DMA12_CONFIG 0xFFC01D08

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#define DMA12_X_COUNT 0xFFC01D10

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#define DMA12_X_MODIFY 0xFFC01D14

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#define DMA12_Y_COUNT 0xFFC01D18

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#define DMA12_Y_MODIFY 0xFFC01D1C

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#define DMA12_CURR_DESC_PTR 0xFFC01D20

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#define DMA12_CURR_ADDR 0xFFC01D24

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#define DMA12_IRQ_STATUS 0xFFC01D28

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#define DMA12_PERIPHERAL_MAP 0xFFC01D2C

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#define DMA12_CURR_X_COUNT 0xFFC01D30

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#define DMA12_CURR_Y_COUNT 0xFFC01D38

417

#define DMA13_NEXT_DESC_PTR 0xFFC01D40

418

#define DMA13_START_ADDR 0xFFC01D44

419

#define DMA13_CONFIG 0xFFC01D48

420

#define DMA13_X_COUNT 0xFFC01D50

421

#define DMA13_X_MODIFY 0xFFC01D54

422

#define DMA13_Y_COUNT 0xFFC01D58

423

#define DMA13_Y_MODIFY 0xFFC01D5C

424

#define DMA13_CURR_DESC_PTR 0xFFC01D60

425

#define DMA13_CURR_ADDR 0xFFC01D64

426

#define DMA13_IRQ_STATUS 0xFFC01D68

427

#define DMA13_PERIPHERAL_MAP 0xFFC01D6C

428

#define DMA13_CURR_X_COUNT 0xFFC01D70

429

#define DMA13_CURR_Y_COUNT 0xFFC01D78

430

#define DMA14_NEXT_DESC_PTR 0xFFC01D80

431

#define DMA14_START_ADDR 0xFFC01D84

432

#define DMA14_CONFIG 0xFFC01D88

433

#define DMA14_X_COUNT 0xFFC01D90

434

#define DMA14_X_MODIFY 0xFFC01D94

435

#define DMA14_Y_COUNT 0xFFC01D98

436

#define DMA14_Y_MODIFY 0xFFC01D9C

437

#define DMA14_CURR_DESC_PTR 0xFFC01DA0

438

#define DMA14_CURR_ADDR 0xFFC01DA4

439

#define DMA14_IRQ_STATUS 0xFFC01DA8

440

#define DMA14_PERIPHERAL_MAP 0xFFC01DAC

441

#define DMA14_CURR_X_COUNT 0xFFC01DB0

442

#define DMA14_CURR_Y_COUNT 0xFFC01DB8

443

#define DMA15_NEXT_DESC_PTR 0xFFC01DC0

444

#define DMA15_START_ADDR 0xFFC01DC4

445

#define DMA15_CONFIG 0xFFC01DC8

446

#define DMA15_X_COUNT 0xFFC01DD0

447

#define DMA15_X_MODIFY 0xFFC01DD4

448

#define DMA15_Y_COUNT 0xFFC01DD8

449

#define DMA15_Y_MODIFY 0xFFC01DDC

450

#define DMA15_CURR_DESC_PTR 0xFFC01DE0

451

#define DMA15_CURR_ADDR 0xFFC01DE4

452

#define DMA15_IRQ_STATUS 0xFFC01DE8

453

#define DMA15_PERIPHERAL_MAP 0xFFC01DEC

454

#define DMA15_CURR_X_COUNT 0xFFC01DF0

455

#define DMA15_CURR_Y_COUNT 0xFFC01DF8

456

#define DMA16_NEXT_DESC_PTR 0xFFC01E00

457

#define DMA16_START_ADDR 0xFFC01E04

458

#define DMA16_CONFIG 0xFFC01E08

459

#define DMA16_X_COUNT 0xFFC01E10

460

#define DMA16_X_MODIFY 0xFFC01E14

461

#define DMA16_Y_COUNT 0xFFC01E18

462

#define DMA16_Y_MODIFY 0xFFC01E1C

463

#define DMA16_CURR_DESC_PTR 0xFFC01E20

464

#define DMA16_CURR_ADDR 0xFFC01E24

465

#define DMA16_IRQ_STATUS 0xFFC01E28

466

#define DMA16_PERIPHERAL_MAP 0xFFC01E2C

467

#define DMA16_CURR_X_COUNT 0xFFC01E30

468

#define DMA16_CURR_Y_COUNT 0xFFC01E38

469

#define DMA17_NEXT_DESC_PTR 0xFFC01E40

470

#define DMA17_START_ADDR 0xFFC01E44

471

#define DMA17_CONFIG 0xFFC01E48

472

#define DMA17_X_COUNT 0xFFC01E50

473

#define DMA17_X_MODIFY 0xFFC01E54

474

#define DMA17_Y_COUNT 0xFFC01E58

475

#define DMA17_Y_MODIFY 0xFFC01E5C

476

#define DMA17_CURR_DESC_PTR 0xFFC01E60

477

#define DMA17_CURR_ADDR 0xFFC01E64

478

#define DMA17_IRQ_STATUS 0xFFC01E68

479

#define DMA17_PERIPHERAL_MAP 0xFFC01E6C

480

#define DMA17_CURR_X_COUNT 0xFFC01E70

481

#define DMA17_CURR_Y_COUNT 0xFFC01E78

482

#define DMA18_NEXT_DESC_PTR 0xFFC01E80

483

#define DMA18_START_ADDR 0xFFC01E84

484

#define DMA18_CONFIG 0xFFC01E88

485

#define DMA18_X_COUNT 0xFFC01E90

486

#define DMA18_X_MODIFY 0xFFC01E94

487

#define DMA18_Y_COUNT 0xFFC01E98

488

#define DMA18_Y_MODIFY 0xFFC01E9C

489

#define DMA18_CURR_DESC_PTR 0xFFC01EA0

490

#define DMA18_CURR_ADDR 0xFFC01EA4

491

#define DMA18_IRQ_STATUS 0xFFC01EA8

492

#define DMA18_PERIPHERAL_MAP 0xFFC01EAC

493

#define DMA18_CURR_X_COUNT 0xFFC01EB0

494

#define DMA18_CURR_Y_COUNT 0xFFC01EB8

495

#define DMA19_NEXT_DESC_PTR 0xFFC01EC0

496

#define DMA19_START_ADDR 0xFFC01EC4

497

#define DMA19_CONFIG 0xFFC01EC8

498

#define DMA19_X_COUNT 0xFFC01ED0

499

#define DMA19_X_MODIFY 0xFFC01ED4

500

#define DMA19_Y_COUNT 0xFFC01ED8

501

#define DMA19_Y_MODIFY 0xFFC01EDC

502

#define DMA19_CURR_DESC_PTR 0xFFC01EE0

503

#define DMA19_CURR_ADDR 0xFFC01EE4

504

#define DMA19_IRQ_STATUS 0xFFC01EE8

505

#define DMA19_PERIPHERAL_MAP 0xFFC01EEC

506

#define DMA19_CURR_X_COUNT 0xFFC01EF0

507

#define DMA19_CURR_Y_COUNT 0xFFC01EF8

508

#define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00

509

#define MDMA0_D0_START_ADDR 0xFFC00E04

510

#define MDMA0_D0_CONFIG 0xFFC00E08

511

#define MDMA0_D0_X_COUNT 0xFFC00E10

512

#define MDMA0_D0_X_MODIFY 0xFFC00E14

513

#define MDMA0_D0_Y_COUNT 0xFFC00E18

514

#define MDMA0_D0_Y_MODIFY 0xFFC00E1C

515

#define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20

516

#define MDMA0_D0_CURR_ADDR 0xFFC00E24

517

#define MDMA0_D0_IRQ_STATUS 0xFFC00E28

518

#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C

519

#define MDMA0_D0_CURR_X_COUNT 0xFFC00E30

520

#define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38

521

#define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40

522

#define MDMA0_S0_START_ADDR 0xFFC00E44

523

#define MDMA0_S0_CONFIG 0xFFC00E48

524

#define MDMA0_S0_X_COUNT 0xFFC00E50

525

#define MDMA0_S0_X_MODIFY 0xFFC00E54

526

#define MDMA0_S0_Y_COUNT 0xFFC00E58

527

#define MDMA0_S0_Y_MODIFY 0xFFC00E5C

528

#define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60

529

#define MDMA0_S0_CURR_ADDR 0xFFC00E64

530

#define MDMA0_S0_IRQ_STATUS 0xFFC00E68

531

#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C

532

#define MDMA0_S0_CURR_X_COUNT 0xFFC00E70

533

#define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78

534

#define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80

535

#define MDMA0_D1_START_ADDR 0xFFC00E84

536

#define MDMA0_D1_CONFIG 0xFFC00E88

537

#define MDMA0_D1_X_COUNT 0xFFC00E90

538

#define MDMA0_D1_X_MODIFY 0xFFC00E94

539

#define MDMA0_D1_Y_COUNT 0xFFC00E98

540

#define MDMA0_D1_Y_MODIFY 0xFFC00E9C

541

#define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0

542

#define MDMA0_D1_CURR_ADDR 0xFFC00EA4

543

#define MDMA0_D1_IRQ_STATUS 0xFFC00EA8

544

#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC

545

#define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0

546

#define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8

547

#define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0

548

#define MDMA0_S1_START_ADDR 0xFFC00EC4

549

#define MDMA0_S1_CONFIG 0xFFC00EC8

550

#define MDMA0_S1_X_COUNT 0xFFC00ED0

551

#define MDMA0_S1_X_MODIFY 0xFFC00ED4

552

#define MDMA0_S1_Y_COUNT 0xFFC00ED8

553

#define MDMA0_S1_Y_MODIFY 0xFFC00EDC

554

#define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0

555

#define MDMA0_S1_CURR_ADDR 0xFFC00EE4

556

#define MDMA0_S1_IRQ_STATUS 0xFFC00EE8

557

#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC

558

#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0

559

#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8

560

#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00

561

#define MDMA1_D0_START_ADDR 0xFFC01F04

562

#define MDMA1_D0_CONFIG 0xFFC01F08

563

#define MDMA1_D0_X_COUNT 0xFFC01F10

564

#define MDMA1_D0_X_MODIFY 0xFFC01F14

565

#define MDMA1_D0_Y_COUNT 0xFFC01F18

566

#define MDMA1_D0_Y_MODIFY 0xFFC01F1C

567

#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20

568

#define MDMA1_D0_CURR_ADDR 0xFFC01F24

569

#define MDMA1_D0_IRQ_STATUS 0xFFC01F28

570

#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C

571

#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30

572

#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38

573

#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40

574

#define MDMA1_S0_START_ADDR 0xFFC01F44

575

#define MDMA1_S0_CONFIG 0xFFC01F48

576

#define MDMA1_S0_X_COUNT 0xFFC01F50

577

#define MDMA1_S0_X_MODIFY 0xFFC01F54

578

#define MDMA1_S0_Y_COUNT 0xFFC01F58

579

#define MDMA1_S0_Y_MODIFY 0xFFC01F5C

580

#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60

581

#define MDMA1_S0_CURR_ADDR 0xFFC01F64

582

#define MDMA1_S0_IRQ_STATUS 0xFFC01F68

583

#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C

584

#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70

585

#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78

586

#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80

587

#define MDMA1_D1_START_ADDR 0xFFC01F84

588

#define MDMA1_D1_CONFIG 0xFFC01F88

589

#define MDMA1_D1_X_COUNT 0xFFC01F90

590

#define MDMA1_D1_X_MODIFY 0xFFC01F94

591

#define MDMA1_D1_Y_COUNT 0xFFC01F98

592

#define MDMA1_D1_Y_MODIFY 0xFFC01F9C

593

#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0

594

#define MDMA1_D1_CURR_ADDR 0xFFC01FA4

595

#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8

596

#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC

597

#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0

598

#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8

599

#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0

600

#define MDMA1_S1_START_ADDR 0xFFC01FC4

601

#define MDMA1_S1_CONFIG 0xFFC01FC8

602

#define MDMA1_S1_X_COUNT 0xFFC01FD0

603

#define MDMA1_S1_X_MODIFY 0xFFC01FD4

604

#define MDMA1_S1_Y_COUNT 0xFFC01FD8

605

#define MDMA1_S1_Y_MODIFY 0xFFC01FDC

606

#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0

607

#define MDMA1_S1_CURR_ADDR 0xFFC01FE4

608

#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8

609

#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC

610

#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0

611

#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8

612

#define PPI_CONTROL 0xFFC01000

613

#define PPI_STATUS 0xFFC01004

614

#define PPI_DELAY 0xFFC0100C

615

#define PPI_COUNT 0xFFC01008

616

#define PPI_FRAME 0xFFC01010

617

#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */

618

#define TWI0_CONTROL 0xFFC01404 /* TWIO Master Internal Time Reference Register */

619

#define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */

620

#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */

621

#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */

622

#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */

623

#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */

624

#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */

625

#define TWI0_INT_STAT 0xFFC01420 /* TWIO Master Interrupt Register */

626

#define TWI0_INT_MASK 0xFFC01424 /* TWIO Master Interrupt Mask Register */

627

#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */

628

#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */

629

#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */

630

#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */

631

#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */

632

#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */

633

#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */

634

#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */

635

#define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */

636

#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */

637

#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */

638

#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */

639

#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */

640

#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */

641

#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */

642

#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */

643

#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */

644

#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */

645

#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */

646

#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */

647

#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */

648

#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */

649

#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */

650

#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */

651

#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */

652

#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */

653

#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */

654

#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */

655

#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */

656

#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */

657

#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */

658

#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */

659

#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */

660

#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */

661

#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */

662

#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */

663

#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */

664

#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */

665

#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */

666

#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */

667

#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */

668

#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */

669

#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */

670

#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */

671

#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */

672

#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */

673

#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */

674

#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */

675

#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */

676

#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */

677

#define CAN_DEBUG 0xFFC02A88 /* Config register */

678

#define CAN_STATUS 0xFFC02A8C /* Global Status Register */

679

#define CAN_CEC 0xFFC02A90 /* Error Counter Register */

680

#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */

681

#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */

682

#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */

683

#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */

684

#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */

685

#define CAN_VERSION 0xFFC02AA8 /* Version Code Register */

686

#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */

687

#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */

688

#define CAN_ESR 0xFFC02AB4 /* Error Status Register */

689

#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */

690

#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */

691

#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */

692

#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */

693

#define CAN_VERSION2 0xFFC02AD4 /* Version Code Register 2 */

694

#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */

695

#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */

696

#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */

697

#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */

698

#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */

699

#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */

700

#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */

701

#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */

702

#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */

703

#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */

704

#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */

705

#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */

706

#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */

707

#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */

708

#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */

709

#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */

710

#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */

711

#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */

712

#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */

713

#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */

714

#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */

715

#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */

716

#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */

717

#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */

718

#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */

719

#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */

720

#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */

721

#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */

722

#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */

723

#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */

724

#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */

725

#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */

726

#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */

727

#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */

728

#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */

729

#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */

730

#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */

731

#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */

732

#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */

733

#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */

734

#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */

735

#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */

736

#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */

737

#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */

738

#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */

739

#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */

740

#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */

741

#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */

742

#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */

743

#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */

744

#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */

745

#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */

746

#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */

747

#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */

748

#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */

749

#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */

750

#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */

751

#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */

752

#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */

753

#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */

754

#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */

755

#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */

756

#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */

757

#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */

758

#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */

759

#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */

760

#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */

761

#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */

762

#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */

763

#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */

764

#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */

765

#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */

766

#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */

767

#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */

768

#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */

769

#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */

770

#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */

771

#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */

772

#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */

773

#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */

774

#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */

775

#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */

776

#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */

777

#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */

778

#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */

779

#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */

780

#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */

781

#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */

782

#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */

783

#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */

784

#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */

785

#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */

786

#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */

787

#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */

788

#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */

789

#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */

790

#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */

791

#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */

792

#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */

793

#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */

794

#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */

795

#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */

796

#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */

797

#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */

798

#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */

799

#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */

800

#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */

801

#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */

802

#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */

803

#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */

804

#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */

805

#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */

806

#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */

807

#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */

808

#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */

809

#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */

810

#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */

811

#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */

812

#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */

813

#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */

814

#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */

815

#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */

816

#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */

817

#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */

818

#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */

819

#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */

820

#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */

821

#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */

822

#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */

823

#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */

824

#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */

825

#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */

826

#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */

827

#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */

828

#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */

829

#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */

830

#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */

831

#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */

832

#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */

833

#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */

834

#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */

835

#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */

836

#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */

837

#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */

838

#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */

839

#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */

840

#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */

841

#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */

842

#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */

843

#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */

844

#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */

845

#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */

846

#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */

847

#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */

848

#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */

849

#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */

850

#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */

851

#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */

852

#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */

853

#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */

854

#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */

855

#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */

856

#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */

857

#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */

858

#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */

859

#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */

860

#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */

861

#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */

862

#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */

863

#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */

864

#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */

865

#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */

866

#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */

867

#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */

868

#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */

869

#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */

870

#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */

871

#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */

872

#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */

873

#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */

874

#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */

875

#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */

876

#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */

877

#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */

878

#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */

879

#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */

880

#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */

881

#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */

882

#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */

883

#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */

884

#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */

885

#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */

886

#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */

887

#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */

888

#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */

889

#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */

890

#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */

891

#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */

892

#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */

893

#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */

894

#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */

895

#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */

896

#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */

897

#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */

898

#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */

899

#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */

900

#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */

901

#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */

902

#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */

903

#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */

904

#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */

905

#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */

906

#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */

907

#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */

908

#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */

909

#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */

910

#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */

911

#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */

912

#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */

913

#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */

914

#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */

915

#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */

916

#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */

917

#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */

918

#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */

919

#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */

920

#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */

921

#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */

922

#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */

923

#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */

924

#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */

925

#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */

926

#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */

927

#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */

928

#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */

929

#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */

930

#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */

931

#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */

932

#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */

933

#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */

934

#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */

935

#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */

936

#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */

937

#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */

938

#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */

939

#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */

940

#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */

941

#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */

942

#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */

943

#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */

944

#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */

945

#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */

946

#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */

947

#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */

948

#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */

949

#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */

950

#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */

951

#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */

952

#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */

953

#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */

954

#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */

955

#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */

956

#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */

957

#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */

958

#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */

959

#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */

960

#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */

961

#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */

962

#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */

963

#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */

964

#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */

965

#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */

966

#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */

967

#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */

968

#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */

969

#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */

970

#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */

971

#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */

972

#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */

973

#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */

974

#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */

975

#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */

976

#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */

977

#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */

978

#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */

979

#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */

980

#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */

981

#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */

982

#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */

983

#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */

984

#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */

985

#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */

986

#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */

987

#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */

988

#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */

989

#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */

990

#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */

991

#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */

992

#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */

993

#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */

994

#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */

995

#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */

996

#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */

997

#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */

998

#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */

999

#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */

1000

#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */

1001

#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */

1002

#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */

1003

#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */

1004

#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */

1005

#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */

1006

#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */

1007

#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */

1008

#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */

1009

#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */

1010

#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */

1011

#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */

1012

#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */

1013

#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */

1014

1015

#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */

1016

#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)

1017

#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)

1018

#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */

1019

#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)

1020

#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)

1021

#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */

1022

#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)

1023

#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)

Mike Frysinger

5662611

2008-08-07 13:10:41 -0400

[diff] [blame]

1024

1025

#endif /* __BFIN_DEF_ADSP_BF538_proc__ */