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git01.mediatek.com / filogic / uboot / a75325e52b2d1aff70e39b7700a3d43acb3c96c8 / . / arch / arm / mach-tegra / tegra20 / pinmux.c
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]2/*
3 * Copyright (c) 2011 The Chromium OS Authors.
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]4 */
5
Allen Martin55d98a12012-08-31 08:30:00 +0000[diff] [blame]6/* Tegra20 pin multiplexing functions */
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]7
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]8#include <common.h>
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]9#include <asm/io.h>
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]10#include <asm/arch/pinmux.h>
Simon Glassfa516f62011-08-30 06:23:14 +0000[diff] [blame]11
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]12/*
13 * This defines the order of the pin mux control bits in the registers. For
14 * some reason there is no correspendence between the tristate, pin mux and
15 * pullup/pulldown registers.
16 */
17enum pmux_ctlid {
18 /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
19 MUXCTL_UAA,
20 MUXCTL_UAB,
21 MUXCTL_UAC,
22 MUXCTL_UAD,
23 MUXCTL_UDA,
24 MUXCTL_RESERVED5,
25 MUXCTL_ATE,
26 MUXCTL_RM,
27
28 MUXCTL_ATB,
29 MUXCTL_RESERVED9,
30 MUXCTL_ATD,
31 MUXCTL_ATC,
32 MUXCTL_ATA,
33 MUXCTL_KBCF,
34 MUXCTL_KBCE,
35 MUXCTL_SDMMC1,
36
37 /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
38 MUXCTL_GMA,
39 MUXCTL_GMC,
40 MUXCTL_HDINT,
41 MUXCTL_SLXA,
42 MUXCTL_OWC,
43 MUXCTL_SLXC,
44 MUXCTL_SLXD,
45 MUXCTL_SLXK,
46
47 MUXCTL_UCA,
48 MUXCTL_UCB,
49 MUXCTL_DTA,
50 MUXCTL_DTB,
51 MUXCTL_RESERVED28,
52 MUXCTL_DTC,
53 MUXCTL_DTD,
54 MUXCTL_DTE,
55
56 /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
57 MUXCTL_DDC,
58 MUXCTL_CDEV1,
59 MUXCTL_CDEV2,
60 MUXCTL_CSUS,
61 MUXCTL_I2CP,
62 MUXCTL_KBCA,
63 MUXCTL_KBCB,
64 MUXCTL_KBCC,
65
66 MUXCTL_IRTX,
67 MUXCTL_IRRX,
68 MUXCTL_DAP1,
69 MUXCTL_DAP2,
70 MUXCTL_DAP3,
71 MUXCTL_DAP4,
72 MUXCTL_GMB,
73 MUXCTL_GMD,
74
75 /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
76 MUXCTL_GME,
77 MUXCTL_GPV,
78 MUXCTL_GPU,
79 MUXCTL_SPDO,
80 MUXCTL_SPDI,
81 MUXCTL_SDB,
82 MUXCTL_SDC,
83 MUXCTL_SDD,
84
85 MUXCTL_SPIH,
86 MUXCTL_SPIG,
87 MUXCTL_SPIF,
88 MUXCTL_SPIE,
89 MUXCTL_SPID,
90 MUXCTL_SPIC,
91 MUXCTL_SPIB,
92 MUXCTL_SPIA,
93
94 /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
95 MUXCTL_LPW0,
96 MUXCTL_LPW1,
97 MUXCTL_LPW2,
98 MUXCTL_LSDI,
99 MUXCTL_LSDA,
100 MUXCTL_LSPI,
101 MUXCTL_LCSN,
102 MUXCTL_LDC,
103
104 MUXCTL_LSCK,
105 MUXCTL_LSC0,
106 MUXCTL_LSC1,
107 MUXCTL_LHS,
108 MUXCTL_LVS,
109 MUXCTL_LM0,
110 MUXCTL_LM1,
111 MUXCTL_LVP0,
112
113 /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
114 MUXCTL_LD0,
115 MUXCTL_LD1,
116 MUXCTL_LD2,
117 MUXCTL_LD3,
118 MUXCTL_LD4,
119 MUXCTL_LD5,
120 MUXCTL_LD6,
121 MUXCTL_LD7,
122
123 MUXCTL_LD8,
124 MUXCTL_LD9,
125 MUXCTL_LD10,
126 MUXCTL_LD11,
127 MUXCTL_LD12,
128 MUXCTL_LD13,
129 MUXCTL_LD14,
130 MUXCTL_LD15,
131
132 /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
133 MUXCTL_LD16,
134 MUXCTL_LD17,
135 MUXCTL_LHP1,
136 MUXCTL_LHP2,
137 MUXCTL_LVP1,
138 MUXCTL_LHP0,
139 MUXCTL_RESERVED102,
140 MUXCTL_LPP,
141
142 MUXCTL_LDI,
143 MUXCTL_PMC,
144 MUXCTL_CRTP,
145 MUXCTL_PTA,
146 MUXCTL_RESERVED108,
147 MUXCTL_KBCD,
148 MUXCTL_GPU7,
149 MUXCTL_DTF,
150
151 MUXCTL_NONE = -1,
152};
153
154/*
155 * And this defines the order of the pullup/pulldown controls which are again
156 * in a different order
157 */
158enum pmux_pullid {
159 /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
160 PUCTL_ATA,
161 PUCTL_ATB,
162 PUCTL_ATC,
163 PUCTL_ATD,
164 PUCTL_ATE,
165 PUCTL_DAP1,
166 PUCTL_DAP2,
167 PUCTL_DAP3,
168
169 PUCTL_DAP4,
170 PUCTL_DTA,
171 PUCTL_DTB,
172 PUCTL_DTC,
173 PUCTL_DTD,
174 PUCTL_DTE,
175 PUCTL_DTF,
176 PUCTL_GPV,
177
178 /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
179 PUCTL_RM,
180 PUCTL_I2CP,
181 PUCTL_PTA,
182 PUCTL_GPU7,
183 PUCTL_KBCA,
184 PUCTL_KBCB,
185 PUCTL_KBCC,
186 PUCTL_KBCD,
187
188 PUCTL_SPDI,
189 PUCTL_SPDO,
190 PUCTL_GPSLXAU,
191 PUCTL_CRTP,
192 PUCTL_SLXC,
193 PUCTL_SLXD,
194 PUCTL_SLXK,
195
196 /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
197 PUCTL_CDEV1,
198 PUCTL_CDEV2,
199 PUCTL_SPIA,
200 PUCTL_SPIB,
201 PUCTL_SPIC,
202 PUCTL_SPID,
203 PUCTL_SPIE,
204 PUCTL_SPIF,
205
206 PUCTL_SPIG,
207 PUCTL_SPIH,
208 PUCTL_IRTX,
209 PUCTL_IRRX,
210 PUCTL_GME,
211 PUCTL_RESERVED45,
212 PUCTL_XM2D,
213 PUCTL_XM2C,
214
215 /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
216 PUCTL_UAA,
217 PUCTL_UAB,
218 PUCTL_UAC,
219 PUCTL_UAD,
220 PUCTL_UCA,
221 PUCTL_UCB,
222 PUCTL_LD17,
223 PUCTL_LD19_18,
224
225 PUCTL_LD21_20,
226 PUCTL_LD23_22,
227 PUCTL_LS,
228 PUCTL_LC,
229 PUCTL_CSUS,
230 PUCTL_DDRC,
231 PUCTL_SDC,
232 PUCTL_SDD,
233
234 /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
235 PUCTL_KBCF,
236 PUCTL_KBCE,
237 PUCTL_PMCA,
238 PUCTL_PMCB,
239 PUCTL_PMCC,
240 PUCTL_PMCD,
241 PUCTL_PMCE,
242 PUCTL_CK32,
243
244 PUCTL_UDA,
245 PUCTL_SDMMC1,
246 PUCTL_GMA,
247 PUCTL_GMB,
248 PUCTL_GMC,
249 PUCTL_GMD,
250 PUCTL_DDC,
251 PUCTL_OWC,
252
253 PUCTL_NONE = -1
254};
255
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]256/* Convenient macro for defining pin group properties */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]257#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]258 { \
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]259 .funcs = { \
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]260 PMUX_FUNC_ ## f0, \
261 PMUX_FUNC_ ## f1, \
262 PMUX_FUNC_ ## f2, \
263 PMUX_FUNC_ ## f3, \
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]264 }, \
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]265 .ctl_id = mux, \
266 .pull_id = pupd \
267 }
268
269/* A normal pin group where the mux name and pull-up name match */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]270#define PIN(pingrp, f0, f1, f2, f3) \
271 PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]272
273/* A pin group where the pull-up name doesn't have a 1-1 mapping */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]274#define PINP(pingrp, f0, f1, f2, f3, pupd) \
275 PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]276
277/* A pin group number which is not used */
278#define PIN_RESERVED \
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]279 PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
Stephen Warren8569b3a2014-03-21 12:28:51 -0600[diff] [blame]280
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]281#define DRVGRP(drvgrp) \
282 PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]283
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]284static const struct pmux_pingrp_desc tegra20_pingroups[] = {
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]285 PIN(ATA, IDE, NAND, GMI, RSVD4),
286 PIN(ATB, IDE, NAND, GMI, SDIO4),
287 PIN(ATC, IDE, NAND, GMI, SDIO4),
288 PIN(ATD, IDE, NAND, GMI, SDIO4),
289 PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC),
290 PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4),
291 PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
292 PIN(DAP1, DAP1, RSVD2, GMI, SDIO2),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]293
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]294 PIN(DAP2, DAP2, TWC, RSVD3, GMI),
295 PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4),
296 PIN(DAP4, DAP4, RSVD2, GMI, RSVD4),
297 PIN(DTA, RSVD1, SDIO2, VI, RSVD4),
298 PIN(DTB, RSVD1, RSVD2, VI, SPI1),
299 PIN(DTC, RSVD1, RSVD2, VI, RSVD4),
300 PIN(DTD, RSVD1, SDIO2, VI, RSVD4),
301 PIN(DTE, RSVD1, RSVD2, VI, SPI1),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]302
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]303 PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU),
304 PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
305 PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4),
306 PIN(IRTX, UARTA, UARTB, GMI, SPI4),
307 PIN(IRRX, UARTA, UARTB, GMI, SPI4),
308 PIN(KBCB, KBC, NAND, SDIO2, MIO),
309 PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL),
310 PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]311
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]312 PIN(PTA, I2C2, HDMI, GMI, RSVD4),
313 PIN(RM, I2C, RSVD2, RSVD3, RSVD4),
314 PIN(KBCE, KBC, NAND, OWR, RSVD4),
315 PIN(KBCF, KBC, NAND, TRACE, MIO),
316 PIN(GMA, UARTE, SPI3, GMI, SDIO4),
317 PIN(GMC, UARTD, SPI4, GMI, SFLASH),
318 PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA),
319 PIN(OWC, OWR, RSVD2, RSVD3, RSVD4),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]320
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]321 PIN(GME, RSVD1, DAP5, GMI, SDIO4),
322 PIN(SDC, PWM, TWC, SDIO3, SPI3),
323 PIN(SDD, UARTA, PWM, SDIO3, SPI3),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]324 PIN_RESERVED,
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]325 PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
326 PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2),
327 PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2),
328 PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]329
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]330 PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2),
331 PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2),
332 PIN(SPIA, SPI1, SPI2, SPI3, GMI),
333 PIN(SPIB, SPI1, SPI2, SPI3, GMI),
334 PIN(SPIC, SPI1, SPI2, SPI3, GMI),
335 PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI),
336 PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI),
337 PIN(SPIF, SPI3, SPI1, SPI2, RSVD4),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]338
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]339 PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C),
340 PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C),
341 PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI),
342 PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI),
343 PIN(UAC, OWR, RSVD2, RSVD3, RSVD4),
344 PIN(UAD, UARTB, SPDIF, UARTA, SPI4),
345 PIN(UCA, UARTC, RSVD2, GMI, RSVD4),
346 PIN(UCB, UARTC, PWM, GMI, RSVD4),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]347
348 PIN_RESERVED,
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]349 PIN(ATE, IDE, NAND, GMI, RSVD4),
350 PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]351 PIN_RESERVED,
352 PIN_RESERVED,
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]353 PIN(GMB, IDE, NAND, GMI, GMI_INT),
354 PIN(GMD, RSVD1, NAND, GMI, SFLASH),
355 PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]356
357 /* 64 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]358 PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17),
359 PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17),
360 PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17),
361 PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17),
362 PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17),
363 PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17),
364 PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17),
365 PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]366
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]367 PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17),
368 PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17),
369 PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17),
370 PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17),
371 PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17),
372 PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17),
373 PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17),
374 PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]375
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]376 PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17),
377 PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17),
378 PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
379 PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
380 PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
381 PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC),
382 PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
383 PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]384
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]385 PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC),
386 PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC),
387 PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC),
388 PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC),
389 PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS),
390 PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS),
391 PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS),
392 PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]393
394 /* 96 */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]395 PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC),
396 PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS),
397 PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS),
398 PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS),
399 PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS),
400 PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS),
401 PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
402 PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]403
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]404 PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]405 PIN_RESERVED,
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]406 PIN(KBCD, KBC, NAND, SDIO2, MIO),
407 PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4),
408 PIN(DTF, I2C3, RSVD2, VI, RSVD4),
409 PIN(UDA, SPI1, RSVD2, UARTD, ULPI),
410 PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4),
411 PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]412
413 /* these pin groups only have pullup and pull down control */
Stephen Warrenf27f4e82014-03-21 12:28:58 -0600[diff] [blame]414 DRVGRP(CK32),
415 DRVGRP(DDRC),
416 DRVGRP(PMCA),
417 DRVGRP(PMCB),
418 DRVGRP(PMCC),
419 DRVGRP(PMCD),
420 DRVGRP(PMCE),
421 DRVGRP(XM2C),
422 DRVGRP(XM2D),
Simon Glassb70bbf12011-09-21 12:40:06 +0000[diff] [blame]423};
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]424const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;