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git01.mediatek.com / filogic / uboot / a75325e52b2d1aff70e39b7700a3d43acb3c96c8 / . / arch / arm / dts / zynqmp-zcu216-revA.dts
blob: f3b5edfeb4234f1ea3a8036f41a4182a3ea4c587 [file] [log] [blame]
Michal Simekc13291f2019-08-06 12:07:10 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU216
4 *
Michal Simek4f1b7f62020-02-18 08:38:06 +0100[diff] [blame]5 * (C) Copyright 2017 - 2020, Xilinx, Inc.
Michal Simekc13291f2019-08-06 12:07:10 +0200[diff] [blame]6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17
18/ {
19 model = "ZynqMP ZCU216 RevA";
20 compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp";
21
22 aliases {
23 ethernet0 = &gem3;
24 gpio0 = &gpio;
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 mmc0 = &sdhci1;
28 rtc0 = &rtc;
29 serial0 = &uart0;
30 serial1 = &dcc;
31 spi0 = &qspi;
32 usb0 = &usb0;
33 };
34
35 chosen {
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
38 xlnx,eeprom = <&eeprom>;
39 };
40
41 memory@0 {
42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44 };
45
46 gpio-keys {
47 compatible = "gpio-keys";
48 autorepeat;
49 sw19 {
50 label = "sw19";
51 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
52 linux,code = <KEY_DOWN>;
Michal Simekf701e192020-02-18 12:06:14 +0100[diff] [blame]53 wakeup-source;
Michal Simekc13291f2019-08-06 12:07:10 +0200[diff] [blame]54 autorepeat;
55 };
56 };
57
58 leds {
59 compatible = "gpio-leds";
60 heartbeat_led {
61 label = "heartbeat";
62 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
63 linux,default-trigger = "heartbeat";
64 };
65 };
66
67 ina226-vccint {
68 compatible = "iio-hwmon";
69 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
70 };
71 ina226-vccint-io-bram-ps {
72 compatible = "iio-hwmon";
73 io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
74 };
75 ina226-vcc1v8 {
76 compatible = "iio-hwmon";
77 io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
78 };
79 ina226-vcc1v2 {
80 compatible = "iio-hwmon";
81 io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
82 };
83 ina226-vadj-fmc {
84 compatible = "iio-hwmon";
85 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
86 };
87 ina226-mgtavcc {
88 compatible = "iio-hwmon";
89 io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
90 };
91 ina226-mgt1v2 {
92 compatible = "iio-hwmon";
93 io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
94 };
95 ina226-mgt1v8 {
96 compatible = "iio-hwmon";
97 io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
98 };
99 ina226-vccint-ams {
100 compatible = "iio-hwmon";
101 io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
102 };
103 ina226-dac-avtt {
104 compatible = "iio-hwmon";
105 io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
106 };
107 ina226-dac-avccaux {
108 compatible = "iio-hwmon";
109 io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
110 };
111 ina226-adc-avcc {
112 compatible = "iio-hwmon";
113 io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
114 };
115 ina226-adc-avccaux {
116 compatible = "iio-hwmon";
117 io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
118 };
119 ina226-dac-avcc {
120 compatible = "iio-hwmon";
121 io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
122 };
123};
124
125&dcc {
126 status = "okay";
127};
128
129&fpd_dma_chan1 {
130 status = "okay";
131};
132
133&fpd_dma_chan2 {
134 status = "okay";
135};
136
137&fpd_dma_chan3 {
138 status = "okay";
139};
140
141&fpd_dma_chan4 {
142 status = "okay";
143};
144
145&fpd_dma_chan5 {
146 status = "okay";
147};
148
149&fpd_dma_chan6 {
150 status = "okay";
151};
152
153&fpd_dma_chan7 {
154 status = "okay";
155};
156
157&fpd_dma_chan8 {
158 status = "okay";
159};
160
161&gem3 {
162 status = "okay";
163 phy-handle = <&phy0>;
164 phy-mode = "rgmii-id";
165 phy0: ethernet-phy@c {
166 reg = <0xc>;
167 ti,rx-internal-delay = <0x8>;
168 ti,tx-internal-delay = <0xa>;
169 ti,fifo-depth = <0x1>;
170 ti,dp83867-rxctrl-strap-quirk;
171 };
172};
173
174&gpio {
175 status = "okay";
176 gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
177 "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
178 "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
179 "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
180 "", "", "BUTTON", "LED", "", /* 20 - 24 */
181 "", "PMU_INPUT", "", "", "", /* 25 - 29 */
182 "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
183 "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
184 "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
185 "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
186 "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
187 "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
188 "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
189 "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
190 "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
191 "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
192 "", "", /* 78 - 79 */
193 "", "", "", "", "", /* 80 - 84 */
194 "", "", "", "", "", /* 85 -89 */
195 "", "", "", "", "", /* 90 - 94 */
196 "", "", "", "", "", /* 95 - 99 */
197 "", "", "", "", "", /* 100 - 104 */
198 "", "", "", "", "", /* 105 - 109 */
199 "", "", "", "", "", /* 110 - 114 */
200 "", "", "", "", "", /* 115 - 119 */
201 "", "", "", "", "", /* 120 - 124 */
202 "", "", "", "", "", /* 125 - 129 */
203 "", "", "", "", "", /* 130 - 134 */
204 "", "", "", "", "", /* 135 - 139 */
205 "", "", "", "", "", /* 140 - 144 */
206 "", "", "", "", "", /* 145 - 149 */
207 "", "", "", "", "", /* 150 - 154 */
208 "", "", "", "", "", /* 155 - 159 */
209 "", "", "", "", "", /* 160 - 164 */
210 "", "", "", "", "", /* 165 - 169 */
211 "", "", "", ""; /* 170 - 174 */
212};
213
214&gpu {
215 status = "okay";
216};
217
218&i2c0 {
219 status = "okay";
220 clock-frequency = <400000>;
221
222 tca6416_u15: gpio@20 { /* u15 */
223 compatible = "ti,tca6416";
224 reg = <0x20>;
225 gpio-controller; /* interrupt not connected */
226 #gpio-cells = <2>;
227 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */
228 "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
229 "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
230 "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
231 };
232
233 i2c-mux@75 { /* u17 */
234 compatible = "nxp,pca9544";
235 #address-cells = <1>;
236 #size-cells = <0>;
237 reg = <0x75>;
238 i2c@0 {
239 #address-cells = <1>;
240 #size-cells = <0>;
241 reg = <0>;
242 /* PS_PMBUS */
243 /* PMBUS_ALERT done via pca9544 */
244 vccint: ina226@40 { /* u65 */
245 compatible = "ti,ina226";
246 #io-channel-cells = <1>;
247 label = "ina226-vccint";
248 reg = <0x40>;
249 shunt-resistor = <5000>;
250 };
251 vccint_io_bram_ps: ina226@41 { /* u57 */
252 compatible = "ti,ina226";
253 #io-channel-cells = <1>;
254 label = "ina226-vccint-io-bram-ps";
255 reg = <0x41>;
Michal Simek4cb602c2019-11-25 09:55:28 +0100[diff] [blame]256 shunt-resistor = <5000>;
Michal Simekc13291f2019-08-06 12:07:10 +0200[diff] [blame]257 };
258 vcc1v8: ina226@42 { /* u60 */
259 compatible = "ti,ina226";
260 #io-channel-cells = <1>;
261 label = "ina226-vcc1v8";
262 reg = <0x42>;
263 shunt-resistor = <2000>;
264 };
265 vcc1v2: ina226@43 { /* u58 */
266 compatible = "ti,ina226";
267 #io-channel-cells = <1>;
268 label = "ina226-vcc1v2";
269 reg = <0x43>;
270 shunt-resistor = <5000>;
271 };
272 vadj_fmc: ina226@45 { /* u62 */
273 compatible = "ti,ina226";
274 #io-channel-cells = <1>;
275 label = "ina226-vadj-fmc";
276 reg = <0x45>;
277 shunt-resistor = <5000>;
278 };
279 mgtavcc: ina226@46 { /* u67 */
280 compatible = "ti,ina226";
281 #io-channel-cells = <1>;
282 label = "ina226-mgtavcc";
283 reg = <0x46>;
284 shunt-resistor = <2000>;
285 };
286 mgt1v2: ina226@47 { /* u63 */
287 compatible = "ti,ina226";
288 #io-channel-cells = <1>;
289 label = "ina226-mgt1v2";
290 reg = <0x47>;
291 shunt-resistor = <5000>;
292 };
293 mgt1v8: ina226@48 { /* u64 */
294 compatible = "ti,ina226";
295 #io-channel-cells = <1>;
296 label = "ina226-mgt1v8";
297 reg = <0x48>;
298 shunt-resistor = <5000>;
299 };
300 vccint_ams: ina226@49 { /* u61 */
301 compatible = "ti,ina226";
302 #io-channel-cells = <1>;
303 label = "ina226-vccint-ams";
304 reg = <0x49>;
Michal Simek4cb602c2019-11-25 09:55:28 +0100[diff] [blame]305 shunt-resistor = <5000>;
Michal Simekc13291f2019-08-06 12:07:10 +0200[diff] [blame]306 };
307 dac_avtt: ina226@4a { /* u59 */
308 compatible = "ti,ina226";
309 #io-channel-cells = <1>;
310 label = "ina226-dac-avtt";
311 reg = <0x4a>;
312 shunt-resistor = <5000>;
313 };
314 dac_avccaux: ina226@4b { /* u124 */
315 compatible = "ti,ina226";
316 #io-channel-cells = <1>;
317 label = "ina226-dac-avccaux";
318 reg = <0x4b>;
319 shunt-resistor = <5000>;
320 };
321 adc_avcc: ina226@4c { /* u75 */
322 compatible = "ti,ina226";
323 #io-channel-cells = <1>;
324 label = "ina226-adc-avcc";
325 reg = <0x4c>;
326 shunt-resistor = <5000>;
327 };
328 adc_avccaux: ina226@4d { /* u71 */
329 compatible = "ti,ina226";
330 #io-channel-cells = <1>;
331 label = "ina226-adc-avccaux";
332 reg = <0x4d>;
333 shunt-resistor = <5000>;
334 };
335 dac_avcc: ina226@4e { /* u77 */
336 compatible = "ti,ina226";
337 #io-channel-cells = <1>;
338 label = "ina226-dac-avcc";
339 reg = <0x4e>;
340 shunt-resistor = <5000>;
341 };
342 };
343 i2c@1 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 reg = <1>;
347 /* NC */
348 };
349 i2c@2 {
350 #address-cells = <1>;
351 #size-cells = <0>;
352 reg = <2>;
353 /* u104 - ir35215 0x10/0x40 */
354 /* u127 - ir38164 0x1b/0x4b */
355 /* u112 - ir38164 0x13/0x43 */
356 /* u123 - ir38164 0x1c/0x4c */
357
358 irps5401_44: irps54012@44 { /* IRPS5401 - u53 */
359 #clock-cells = <0>;
360 compatible = "infineon,irps5401";
361 reg = <0x44>; /* i2c addr 0x14 */
362 };
363 irps5401_45: irps54012@45 { /* IRPS5401 - u55 */
364 #clock-cells = <0>;
365 compatible = "infineon,irps5401";
366 reg = <0x45>; /* i2c addr 0x15 */
367 };
368 /* J21 header too */
369
370 };
371 i2c@3 {
372 #address-cells = <1>;
373 #size-cells = <0>;
374 reg = <3>;
375 /* SYSMON */
376 };
377 };
378 /* u38 MPS430 */
379};
380
381&i2c1 {
382 status = "okay";
383 clock-frequency = <400000>;
384
385 i2c-mux@74 {
386 compatible = "nxp,pca9548"; /* u20 */
387 #address-cells = <1>;
388 #size-cells = <0>;
389 reg = <0x74>;
390 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
391 i2c_eeprom: i2c@0 {
392 #address-cells = <1>;
393 #size-cells = <0>;
394 reg = <0>;
395 /*
396 * IIC_EEPROM 1kB memory which uses 256B blocks
397 * where every block has different address.
398 * 0 - 256B address 0x54
399 * 256B - 512B address 0x55
400 * 512B - 768B address 0x56
401 * 768B - 1024B address 0x57
402 */
403 eeprom: eeprom@54 { /* u21 */
Raviteja Narayanam856d52d2019-11-26 18:22:50 +0530[diff] [blame]404 compatible = "atmel,24c128";
Michal Simekc13291f2019-08-06 12:07:10 +0200[diff] [blame]405 reg = <0x54>;
406 };
407 };
408 i2c_si5341: i2c@1 {
409 #address-cells = <1>;
410 #size-cells = <0>;
411 reg = <1>;
412 si5341: clock-generator@36 { /* SI5341 - u43 */
413 compatible = "si5341";
414 reg = <0x36>;
415 };
416
417 };
418 i2c_si570_user_c0: i2c@2 {
419 #address-cells = <1>;
420 #size-cells = <0>;
421 reg = <2>;
422 si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
423 #clock-cells = <0>;
424 compatible = "silabs,si570";
425 reg = <0x5d>;
426 temperature-stability = <50>;
427 factory-fout = <300000000>;
428 clock-frequency = <300000000>;
429 clock-output-names = "si570_user_c0";
430 };
431 };
432 i2c_si570_mgt: i2c@3 {
433 #address-cells = <1>;
434 #size-cells = <0>;
435 reg = <3>;
436 si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
437 #clock-cells = <0>;
438 compatible = "silabs,si570";
439 reg = <0x5d>;
440 temperature-stability = <50>;
441 factory-fout = <156250000>;
442 clock-frequency = <148500000>;
443 clock-output-names = "si570_mgt";
444 };
445 };
446 i2c_8a34001: i2c@4 {
447 #address-cells = <1>;
448 #size-cells = <0>;
449 reg = <4>;
450 /* U409B - 8a34001 */
451 };
452 i2c_clk104: i2c@5 {
453 #address-cells = <1>;
454 #size-cells = <0>;
455 reg = <5>;
456 /* CLK104_SDA */
457 };
458 i2c@6 {
459 #address-cells = <1>;
460 #size-cells = <0>;
461 reg = <6>;
462 /* RFMCP connector */
463 };
464 /* 7 NC */
465 };
466
467 i2c-mux@75 {
468 compatible = "nxp,pca9548"; /* u22 */
469 #address-cells = <1>;
470 #size-cells = <0>;
471 reg = <0x75>;
472 /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
473 i2c@0 {
474 #address-cells = <1>;
475 #size-cells = <0>;
476 reg = <0>;
477 /* FMCP_HSPC_IIC */
478 };
479 i2c_si570_user_c1: i2c@1 {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 reg = <1>;
483 si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
484 #clock-cells = <0>;
485 compatible = "silabs,si570";
486 reg = <0x5d>;
487 temperature-stability = <50>;
488 factory-fout = <300000000>;
489 clock-frequency = <300000000>;
490 clock-output-names = "si570_user_c1";
491 };
492 };
493 i2c@2 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 reg = <2>;
497 /* SYSMON */
498 };
499 i2c@3 {
500 #address-cells = <1>;
501 #size-cells = <0>;
502 reg = <3>;
503 /* DDR4 SODIMM */
504 };
505 i2c@4 {
506 #address-cells = <1>;
507 #size-cells = <0>;
508 reg = <4>;
509 /* SFP3 */
510 };
511 i2c@5 {
512 #address-cells = <1>;
513 #size-cells = <0>;
514 reg = <5>;
515 /* SFP2 */
516 };
517 i2c@6 {
518 #address-cells = <1>;
519 #size-cells = <0>;
520 reg = <6>;
521 /* SFP1 */
522 };
523 i2c@7 {
524 #address-cells = <1>;
525 #size-cells = <0>;
526 reg = <7>;
527 /* SFP0 */
528 };
529 };
530 /* MSP430 */
531};
532
533&qspi {
534 status = "okay";
535 is-dual = <1>;
536 flash@0 {
537 compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
538 #address-cells = <1>;
539 #size-cells = <1>;
540 reg = <0x0>;
541 spi-tx-bus-width = <1>;
542 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
543 spi-max-frequency = <108000000>; /* Based on DC1 spec */
544 };
545};
546
547&rtc {
548 status = "okay";
549};
550
551&sata {
552 status = "okay";
553 /* SATA OOB timing settings */
554 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
555 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
556 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
557 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
558 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
559 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
560 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
561 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
562 phy-names = "sata-phy";
563 phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
564};
565
566/* SD1 with level shifter */
567&sdhci1 {
568 status = "okay";
569 disable-wp;
Manish Naranie2ba0932020-02-13 23:37:30 -0700[diff] [blame]570 /*
571 * This property should be removed for supporting UHS mode
572 */
573 no-1-8-v;
Michal Simekc13291f2019-08-06 12:07:10 +0200[diff] [blame]574 xlnx,mio_bank = <1>;
575};
576
577&serdes {
578 status = "okay";
579};
580
581&uart0 {
582 status = "okay";
583};
584
585/* ULPI SMSC USB3320 */
586&usb0 {
587 status = "okay";
588};
589
590&dwc3_0 {
591 status = "okay";
592 dr_mode = "host";
593 snps,usb3_lpm_capable;
594 phy-names = "usb3-phy";
595 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
596};