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git01.mediatek.com / filogic / uboot / a73b0ec92909de767b540ea6407ddb4ae6abaf08 / . / arch / arm / dts / am33xx.dtsi
blob: 14caee7f0d09fa304925394da2d1a06c61d85811 [file] [log] [blame]
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/pinctrl/am33xx.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am33xx";
18 interrupt-parent = <&intc>;
19
20 aliases {
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]38 };
39
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 cpu@0 {
44 compatible = "arm,cortex-a8";
45 device_type = "cpu";
46 reg = <0>;
47
48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]65 clock-latency = <300000>; /* From omap-cpufreq driver */
66 };
67 };
68
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]74 /*
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]75 * The soc node represents the soc top level view. It is used for IPs
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]86 /*
87 * XXX: Use a flat representation of the AM33XX interconnect.
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]88 * The real AM33XX interconnect network is quite complex. Since
89 * it will not bring real advantage to represent that in DT
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]90 * for the moment, just use a fake OCP bus entry to represent
91 * the whole bus hierarchy.
92 */
93 ocp {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges;
98 ti,hwmods = "l3_main";
99
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]100 l4_wkup: l4_wkup@44c00000 {
101 compatible = "ti,am3-l4-wkup", "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 0x44c00000 0x280000>;
105
106 prcm: prcm@200000 {
107 compatible = "ti,am3-prcm";
108 reg = <0x200000 0x4000>;
109
110 prcm_clocks: clocks {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 };
114
115 prcm_clockdomains: clockdomains {
116 };
117 };
118
119 scm: scm@210000 {
120 compatible = "ti,am3-scm", "simple-bus";
121 reg = <0x210000 0x2000>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges = <0 0x210000 0x2000>;
125
126 am33xx_pinmux: pinmux@800 {
127 compatible = "pinctrl-single";
128 reg = <0x800 0x238>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 pinctrl-single,register-width = <32>;
132 pinctrl-single,function-mask = <0x7f>;
133 };
134
135 scm_conf: scm_conf@0 {
136 compatible = "syscon";
137 reg = <0x0 0x800>;
138 #address-cells = <1>;
139 #size-cells = <1>;
140
141 scm_clocks: clocks {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 };
145 };
146
147 scm_clockdomains: clockdomains {
148 };
149 };
150 };
151
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]152 intc: interrupt-controller@48200000 {
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]153 compatible = "ti,am33xx-intc";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]154 interrupt-controller;
155 #interrupt-cells = <1>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]156 reg = <0x48200000 0x1000>;
157 };
158
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]159 edma: edma@49000000 {
160 compatible = "ti,edma3";
161 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
162 reg = <0x49000000 0x10000>,
163 <0x44e10f90 0x40>;
164 interrupts = <12 13 14>;
165 #dma-cells = <1>;
166 };
167
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]168 gpio0: gpio@44e07000 {
169 compatible = "ti,omap4-gpio";
170 ti,hwmods = "gpio1";
171 gpio-controller;
172 #gpio-cells = <2>;
173 interrupt-controller;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]174 #interrupt-cells = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]175 reg = <0x44e07000 0x1000>;
176 interrupts = <96>;
177 };
178
179 gpio1: gpio@4804c000 {
180 compatible = "ti,omap4-gpio";
181 ti,hwmods = "gpio2";
182 gpio-controller;
183 #gpio-cells = <2>;
184 interrupt-controller;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]185 #interrupt-cells = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]186 reg = <0x4804c000 0x1000>;
187 interrupts = <98>;
188 };
189
190 gpio2: gpio@481ac000 {
191 compatible = "ti,omap4-gpio";
192 ti,hwmods = "gpio3";
193 gpio-controller;
194 #gpio-cells = <2>;
195 interrupt-controller;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]196 #interrupt-cells = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]197 reg = <0x481ac000 0x1000>;
198 interrupts = <32>;
199 };
200
201 gpio3: gpio@481ae000 {
202 compatible = "ti,omap4-gpio";
203 ti,hwmods = "gpio4";
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]207 #interrupt-cells = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]208 reg = <0x481ae000 0x1000>;
209 interrupts = <62>;
210 };
211
212 uart0: serial@44e09000 {
213 compatible = "ti,omap3-uart";
214 ti,hwmods = "uart1";
215 clock-frequency = <48000000>;
216 reg = <0x44e09000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]217 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]218 interrupts = <72>;
219 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]220 dmas = <&edma 26>, <&edma 27>;
221 dma-names = "tx", "rx";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]222 };
223
224 uart1: serial@48022000 {
225 compatible = "ti,omap3-uart";
226 ti,hwmods = "uart2";
227 clock-frequency = <48000000>;
228 reg = <0x48022000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]229 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]230 interrupts = <73>;
231 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]232 dmas = <&edma 28>, <&edma 29>;
233 dma-names = "tx", "rx";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]234 };
235
236 uart2: serial@48024000 {
237 compatible = "ti,omap3-uart";
238 ti,hwmods = "uart3";
239 clock-frequency = <48000000>;
240 reg = <0x48024000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]241 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]242 interrupts = <74>;
243 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]244 dmas = <&edma 30>, <&edma 31>;
245 dma-names = "tx", "rx";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]246 };
247
248 uart3: serial@481a6000 {
249 compatible = "ti,omap3-uart";
250 ti,hwmods = "uart4";
251 clock-frequency = <48000000>;
252 reg = <0x481a6000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]253 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]254 interrupts = <44>;
255 status = "disabled";
256 };
257
258 uart4: serial@481a8000 {
259 compatible = "ti,omap3-uart";
260 ti,hwmods = "uart5";
261 clock-frequency = <48000000>;
262 reg = <0x481a8000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]263 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]264 interrupts = <45>;
265 status = "disabled";
266 };
267
268 uart5: serial@481aa000 {
269 compatible = "ti,omap3-uart";
270 ti,hwmods = "uart6";
271 clock-frequency = <48000000>;
272 reg = <0x481aa000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]273 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]274 interrupts = <46>;
275 status = "disabled";
276 };
277
278 i2c0: i2c@44e0b000 {
279 compatible = "ti,omap4-i2c";
280 #address-cells = <1>;
281 #size-cells = <0>;
282 ti,hwmods = "i2c1";
283 reg = <0x44e0b000 0x1000>;
284 interrupts = <70>;
285 status = "disabled";
286 };
287
288 i2c1: i2c@4802a000 {
289 compatible = "ti,omap4-i2c";
290 #address-cells = <1>;
291 #size-cells = <0>;
292 ti,hwmods = "i2c2";
293 reg = <0x4802a000 0x1000>;
294 interrupts = <71>;
295 status = "disabled";
296 };
297
298 i2c2: i2c@4819c000 {
299 compatible = "ti,omap4-i2c";
300 #address-cells = <1>;
301 #size-cells = <0>;
302 ti,hwmods = "i2c3";
303 reg = <0x4819c000 0x1000>;
304 interrupts = <30>;
305 status = "disabled";
306 };
307
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]308 mmc1: mmc@48060000 {
309 compatible = "ti,omap4-hsmmc";
310 ti,hwmods = "mmc1";
311 ti,dual-volt;
312 ti,needs-special-reset;
313 ti,needs-special-hs-handling;
314 dmas = <&edma 24
315 &edma 25>;
316 dma-names = "tx", "rx";
317 interrupts = <64>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]318 reg = <0x48060000 0x1000>;
319 status = "disabled";
320 };
321
322 mmc2: mmc@481d8000 {
323 compatible = "ti,omap4-hsmmc";
324 ti,hwmods = "mmc2";
325 ti,needs-special-reset;
326 dmas = <&edma 2
327 &edma 3>;
328 dma-names = "tx", "rx";
329 interrupts = <28>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]330 reg = <0x481d8000 0x1000>;
331 status = "disabled";
332 };
333
334 mmc3: mmc@47810000 {
335 compatible = "ti,omap4-hsmmc";
336 ti,hwmods = "mmc3";
337 ti,needs-special-reset;
338 interrupts = <29>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]339 reg = <0x47810000 0x1000>;
340 status = "disabled";
341 };
342
343 hwspinlock: spinlock@480ca000 {
344 compatible = "ti,omap4-hwspinlock";
345 reg = <0x480ca000 0x1000>;
346 ti,hwmods = "spinlock";
347 #hwlock-cells = <1>;
348 };
349
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]350 wdt2: wdt@44e35000 {
351 compatible = "ti,omap3-wdt";
352 ti,hwmods = "wd_timer2";
353 reg = <0x44e35000 0x1000>;
354 interrupts = <91>;
355 };
356
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]357 dcan0: can@481cc000 {
358 compatible = "ti,am3352-d_can";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]359 ti,hwmods = "d_can0";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]360 reg = <0x481cc000 0x2000>;
361 clocks = <&dcan0_fck>;
362 clock-names = "fck";
363 syscon-raminit = <&scm_conf 0x644 0>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]364 interrupts = <52>;
365 status = "disabled";
366 };
367
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]368 dcan1: can@481d0000 {
369 compatible = "ti,am3352-d_can";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]370 ti,hwmods = "d_can1";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]371 reg = <0x481d0000 0x2000>;
372 clocks = <&dcan1_fck>;
373 clock-names = "fck";
374 syscon-raminit = <&scm_conf 0x644 1>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]375 interrupts = <55>;
376 status = "disabled";
377 };
378
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]379 mailbox: mailbox@480C8000 {
380 compatible = "ti,omap4-mailbox";
381 reg = <0x480C8000 0x200>;
382 interrupts = <77>;
383 ti,hwmods = "mailbox";
384 #mbox-cells = <1>;
385 ti,mbox-num-users = <4>;
386 ti,mbox-num-fifos = <8>;
387 mbox_wkupm3: wkup_m3 {
388 ti,mbox-tx = <0 0 0>;
389 ti,mbox-rx = <0 0 3>;
390 };
391 };
392
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]393 timer1: timer@44e31000 {
394 compatible = "ti,am335x-timer-1ms";
395 reg = <0x44e31000 0x400>;
396 interrupts = <67>;
397 ti,hwmods = "timer1";
398 ti,timer-alwon;
399 };
400
401 timer2: timer@48040000 {
402 compatible = "ti,am335x-timer";
403 reg = <0x48040000 0x400>;
404 interrupts = <68>;
405 ti,hwmods = "timer2";
406 };
407
408 timer3: timer@48042000 {
409 compatible = "ti,am335x-timer";
410 reg = <0x48042000 0x400>;
411 interrupts = <69>;
412 ti,hwmods = "timer3";
413 };
414
415 timer4: timer@48044000 {
416 compatible = "ti,am335x-timer";
417 reg = <0x48044000 0x400>;
418 interrupts = <92>;
419 ti,hwmods = "timer4";
420 ti,timer-pwm;
421 };
422
423 timer5: timer@48046000 {
424 compatible = "ti,am335x-timer";
425 reg = <0x48046000 0x400>;
426 interrupts = <93>;
427 ti,hwmods = "timer5";
428 ti,timer-pwm;
429 };
430
431 timer6: timer@48048000 {
432 compatible = "ti,am335x-timer";
433 reg = <0x48048000 0x400>;
434 interrupts = <94>;
435 ti,hwmods = "timer6";
436 ti,timer-pwm;
437 };
438
439 timer7: timer@4804a000 {
440 compatible = "ti,am335x-timer";
441 reg = <0x4804a000 0x400>;
442 interrupts = <95>;
443 ti,hwmods = "timer7";
444 ti,timer-pwm;
445 };
446
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]447 rtc: rtc@44e3e000 {
448 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]449 reg = <0x44e3e000 0x1000>;
450 interrupts = <75
451 76>;
452 ti,hwmods = "rtc";
453 };
454
455 spi0: spi@48030000 {
456 compatible = "ti,omap4-mcspi";
457 #address-cells = <1>;
458 #size-cells = <0>;
459 reg = <0x48030000 0x400>;
460 interrupts = <65>;
461 ti,spi-num-cs = <2>;
462 ti,hwmods = "spi0";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]463 dmas = <&edma 16
464 &edma 17
465 &edma 18
466 &edma 19>;
467 dma-names = "tx0", "rx0", "tx1", "rx1";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]468 status = "disabled";
469 };
470
471 spi1: spi@481a0000 {
472 compatible = "ti,omap4-mcspi";
473 #address-cells = <1>;
474 #size-cells = <0>;
475 reg = <0x481a0000 0x400>;
476 interrupts = <125>;
477 ti,spi-num-cs = <2>;
478 ti,hwmods = "spi1";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]479 dmas = <&edma 42
480 &edma 43
481 &edma 44
482 &edma 45>;
483 dma-names = "tx0", "rx0", "tx1", "rx1";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]484 status = "disabled";
485 };
486
487 usb: usb@47400000 {
488 compatible = "ti,am33xx-usb";
489 reg = <0x47400000 0x1000>;
490 ranges;
491 #address-cells = <1>;
492 #size-cells = <1>;
493 ti,hwmods = "usb_otg_hs";
494 status = "disabled";
495
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]496 usb_ctrl_mod: control@44e10620 {
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]497 compatible = "ti,am335x-usb-ctrl-module";
498 reg = <0x44e10620 0x10
499 0x44e10648 0x4>;
500 reg-names = "phy_ctrl", "wakeup";
501 status = "disabled";
502 };
503
504 usb0_phy: usb-phy@47401300 {
505 compatible = "ti,am335x-usb-phy";
506 reg = <0x47401300 0x100>;
507 reg-names = "phy";
508 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]509 ti,ctrl_mod = <&usb_ctrl_mod>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]510 };
511
512 usb0: usb@47401000 {
513 compatible = "ti,musb-am33xx";
514 status = "disabled";
515 reg = <0x47401400 0x400
516 0x47401000 0x200>;
517 reg-names = "mc", "control";
518
519 interrupts = <18>;
520 interrupt-names = "mc";
521 dr_mode = "otg";
522 mentor,multipoint = <1>;
523 mentor,num-eps = <16>;
524 mentor,ram-bits = <12>;
525 mentor,power = <500>;
526 phys = <&usb0_phy>;
527
528 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
529 &cppi41dma 2 0 &cppi41dma 3 0
530 &cppi41dma 4 0 &cppi41dma 5 0
531 &cppi41dma 6 0 &cppi41dma 7 0
532 &cppi41dma 8 0 &cppi41dma 9 0
533 &cppi41dma 10 0 &cppi41dma 11 0
534 &cppi41dma 12 0 &cppi41dma 13 0
535 &cppi41dma 14 0 &cppi41dma 0 1
536 &cppi41dma 1 1 &cppi41dma 2 1
537 &cppi41dma 3 1 &cppi41dma 4 1
538 &cppi41dma 5 1 &cppi41dma 6 1
539 &cppi41dma 7 1 &cppi41dma 8 1
540 &cppi41dma 9 1 &cppi41dma 10 1
541 &cppi41dma 11 1 &cppi41dma 12 1
542 &cppi41dma 13 1 &cppi41dma 14 1>;
543 dma-names =
544 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
545 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
546 "rx14", "rx15",
547 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
548 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
549 "tx14", "tx15";
550 };
551
552 usb1_phy: usb-phy@47401b00 {
553 compatible = "ti,am335x-usb-phy";
554 reg = <0x47401b00 0x100>;
555 reg-names = "phy";
556 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]557 ti,ctrl_mod = <&usb_ctrl_mod>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]558 };
559
560 usb1: usb@47401800 {
561 compatible = "ti,musb-am33xx";
562 status = "disabled";
563 reg = <0x47401c00 0x400
564 0x47401800 0x200>;
565 reg-names = "mc", "control";
566 interrupts = <19>;
567 interrupt-names = "mc";
568 dr_mode = "otg";
569 mentor,multipoint = <1>;
570 mentor,num-eps = <16>;
571 mentor,ram-bits = <12>;
572 mentor,power = <500>;
573 phys = <&usb1_phy>;
574
575 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
576 &cppi41dma 17 0 &cppi41dma 18 0
577 &cppi41dma 19 0 &cppi41dma 20 0
578 &cppi41dma 21 0 &cppi41dma 22 0
579 &cppi41dma 23 0 &cppi41dma 24 0
580 &cppi41dma 25 0 &cppi41dma 26 0
581 &cppi41dma 27 0 &cppi41dma 28 0
582 &cppi41dma 29 0 &cppi41dma 15 1
583 &cppi41dma 16 1 &cppi41dma 17 1
584 &cppi41dma 18 1 &cppi41dma 19 1
585 &cppi41dma 20 1 &cppi41dma 21 1
586 &cppi41dma 22 1 &cppi41dma 23 1
587 &cppi41dma 24 1 &cppi41dma 25 1
588 &cppi41dma 26 1 &cppi41dma 27 1
589 &cppi41dma 28 1 &cppi41dma 29 1>;
590 dma-names =
591 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
592 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
593 "rx14", "rx15",
594 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
595 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
596 "tx14", "tx15";
597 };
598
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]599 cppi41dma: dma-controller@47402000 {
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]600 compatible = "ti,am3359-cppi41";
601 reg = <0x47400000 0x1000
602 0x47402000 0x1000
603 0x47403000 0x1000
604 0x47404000 0x4000>;
605 reg-names = "glue", "controller", "scheduler", "queuemgr";
606 interrupts = <17>;
607 interrupt-names = "glue";
608 #dma-cells = <2>;
609 #dma-channels = <30>;
610 #dma-requests = <256>;
611 status = "disabled";
612 };
613 };
614
615 epwmss0: epwmss@48300000 {
616 compatible = "ti,am33xx-pwmss";
617 reg = <0x48300000 0x10>;
618 ti,hwmods = "epwmss0";
619 #address-cells = <1>;
620 #size-cells = <1>;
621 status = "disabled";
622 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
623 0x48300180 0x48300180 0x80 /* EQEP */
624 0x48300200 0x48300200 0x80>; /* EHRPWM */
625
626 ecap0: ecap@48300100 {
627 compatible = "ti,am33xx-ecap";
628 #pwm-cells = <3>;
629 reg = <0x48300100 0x80>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]630 interrupts = <31>;
631 interrupt-names = "ecap0";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]632 ti,hwmods = "ecap0";
633 status = "disabled";
634 };
635
636 ehrpwm0: ehrpwm@48300200 {
637 compatible = "ti,am33xx-ehrpwm";
638 #pwm-cells = <3>;
639 reg = <0x48300200 0x80>;
640 ti,hwmods = "ehrpwm0";
641 status = "disabled";
642 };
643 };
644
645 epwmss1: epwmss@48302000 {
646 compatible = "ti,am33xx-pwmss";
647 reg = <0x48302000 0x10>;
648 ti,hwmods = "epwmss1";
649 #address-cells = <1>;
650 #size-cells = <1>;
651 status = "disabled";
652 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
653 0x48302180 0x48302180 0x80 /* EQEP */
654 0x48302200 0x48302200 0x80>; /* EHRPWM */
655
656 ecap1: ecap@48302100 {
657 compatible = "ti,am33xx-ecap";
658 #pwm-cells = <3>;
659 reg = <0x48302100 0x80>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]660 interrupts = <47>;
661 interrupt-names = "ecap1";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]662 ti,hwmods = "ecap1";
663 status = "disabled";
664 };
665
666 ehrpwm1: ehrpwm@48302200 {
667 compatible = "ti,am33xx-ehrpwm";
668 #pwm-cells = <3>;
669 reg = <0x48302200 0x80>;
670 ti,hwmods = "ehrpwm1";
671 status = "disabled";
672 };
673 };
674
675 epwmss2: epwmss@48304000 {
676 compatible = "ti,am33xx-pwmss";
677 reg = <0x48304000 0x10>;
678 ti,hwmods = "epwmss2";
679 #address-cells = <1>;
680 #size-cells = <1>;
681 status = "disabled";
682 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
683 0x48304180 0x48304180 0x80 /* EQEP */
684 0x48304200 0x48304200 0x80>; /* EHRPWM */
685
686 ecap2: ecap@48304100 {
687 compatible = "ti,am33xx-ecap";
688 #pwm-cells = <3>;
689 reg = <0x48304100 0x80>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]690 interrupts = <61>;
691 interrupt-names = "ecap2";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]692 ti,hwmods = "ecap2";
693 status = "disabled";
694 };
695
696 ehrpwm2: ehrpwm@48304200 {
697 compatible = "ti,am33xx-ehrpwm";
698 #pwm-cells = <3>;
699 reg = <0x48304200 0x80>;
700 ti,hwmods = "ehrpwm2";
701 status = "disabled";
702 };
703 };
704
705 mac: ethernet@4a100000 {
706 compatible = "ti,cpsw";
707 ti,hwmods = "cpgmac0";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]708 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
709 clock-names = "fck", "cpts";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]710 cpdma_channels = <8>;
711 ale_entries = <1024>;
712 bd_ram_size = <0x2000>;
713 no_bd_ram = <0>;
714 rx_descs = <64>;
715 mac_control = <0x20>;
716 slaves = <2>;
717 active_slave = <0>;
718 cpts_clock_mult = <0x80000000>;
719 cpts_clock_shift = <29>;
720 reg = <0x4a100000 0x800
721 0x4a101200 0x100>;
722 #address-cells = <1>;
723 #size-cells = <1>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]724 /*
725 * c0_rx_thresh_pend
726 * c0_rx_pend
727 * c0_tx_pend
728 * c0_misc_pend
729 */
730 interrupts = <40 41 42 43>;
731 ranges;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]732 syscon = <&scm_conf>;
733 status = "disabled";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]734
735 davinci_mdio: mdio@4a101000 {
736 compatible = "ti,davinci_mdio";
737 #address-cells = <1>;
738 #size-cells = <0>;
739 ti,hwmods = "davinci_mdio";
740 bus_freq = <1000000>;
741 reg = <0x4a101000 0x100>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]742 status = "disabled";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]743 };
744
745 cpsw_emac0: slave@4a100200 {
746 /* Filled in by U-Boot */
747 mac-address = [ 00 00 00 00 00 00 ];
748 };
749
750 cpsw_emac1: slave@4a100300 {
751 /* Filled in by U-Boot */
752 mac-address = [ 00 00 00 00 00 00 ];
753 };
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]754
755 phy_sel: cpsw-phy-sel@44e10650 {
756 compatible = "ti,am3352-cpsw-phy-sel";
757 reg= <0x44e10650 0x4>;
758 reg-names = "gmii-sel";
759 };
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]760 };
761
762 ocmcram: ocmcram@40300000 {
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]763 compatible = "mmio-sram";
764 reg = <0x40300000 0x10000>; /* 64k */
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]765 };
766
767 wkup_m3: wkup_m3@44d00000 {
768 compatible = "ti,am3353-wkup-m3";
769 reg = <0x44d00000 0x4000 /* M3 UMEM */
770 0x44d80000 0x2000>; /* M3 DMEM */
771 ti,hwmods = "wkup_m3";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]772 ti,no-reset-on-init;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]773 };
774
775 elm: elm@48080000 {
776 compatible = "ti,am3352-elm";
777 reg = <0x48080000 0x2000>;
778 interrupts = <4>;
779 ti,hwmods = "elm";
780 status = "disabled";
781 };
782
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]783 lcdc: lcdc@4830e000 {
784 compatible = "ti,am33xx-tilcdc";
785 reg = <0x4830e000 0x1000>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]786 interrupts = <36>;
787 ti,hwmods = "lcdc";
788 status = "disabled";
789 };
790
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]791 tscadc: tscadc@44e0d000 {
792 compatible = "ti,am3359-tscadc";
793 reg = <0x44e0d000 0x1000>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]794 interrupts = <16>;
795 ti,hwmods = "adc_tsc";
796 status = "disabled";
797
798 tsc {
799 compatible = "ti,am3359-tsc";
800 };
801 am335x_adc: adc {
802 #io-channel-cells = <1>;
803 compatible = "ti,am3359-adc";
804 };
805 };
806
807 gpmc: gpmc@50000000 {
808 compatible = "ti,am3352-gpmc";
809 ti,hwmods = "gpmc";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]810 ti,no-idle-on-init;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]811 reg = <0x50000000 0x2000>;
812 interrupts = <100>;
813 gpmc,num-cs = <7>;
814 gpmc,num-waitpins = <2>;
815 #address-cells = <2>;
816 #size-cells = <1>;
817 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]818 };
819
820 sham: sham@53100000 {
821 compatible = "ti,omap4-sham";
822 ti,hwmods = "sham";
823 reg = <0x53100000 0x200>;
824 interrupts = <109>;
825 dmas = <&edma 36>;
826 dma-names = "rx";
827 };
828
829 aes: aes@53500000 {
830 compatible = "ti,omap4-aes";
831 ti,hwmods = "aes";
832 reg = <0x53500000 0xa0>;
833 interrupts = <103>;
834 dmas = <&edma 6>,
835 <&edma 5>;
836 dma-names = "tx", "rx";
837 };
838
839 mcasp0: mcasp@48038000 {
840 compatible = "ti,am33xx-mcasp-audio";
841 ti,hwmods = "mcasp0";
842 reg = <0x48038000 0x2000>,
843 <0x46000000 0x400000>;
844 reg-names = "mpu", "dat";
845 interrupts = <80>, <81>;
846 interrupt-names = "tx", "rx";
847 status = "disabled";
848 dmas = <&edma 8>,
849 <&edma 9>;
850 dma-names = "tx", "rx";
851 };
852
853 mcasp1: mcasp@4803C000 {
854 compatible = "ti,am33xx-mcasp-audio";
855 ti,hwmods = "mcasp1";
856 reg = <0x4803C000 0x2000>,
857 <0x46400000 0x400000>;
858 reg-names = "mpu", "dat";
859 interrupts = <82>, <83>;
860 interrupt-names = "tx", "rx";
861 status = "disabled";
862 dmas = <&edma 10>,
863 <&edma 11>;
864 dma-names = "tx", "rx";
865 };
866
867 rng: rng@48310000 {
868 compatible = "ti,omap4-rng";
869 ti,hwmods = "rng";
870 reg = <0x48310000 0x2000>;
871 interrupts = <111>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]872 };
873 };
874};
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]875
876/include/ "am33xx-clocks.dtsi"