blob: 7eb1ec9366a786da7b119e2a02d61e908d115cf5 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +05302/*
Priyanka Singhd06adf22020-01-22 10:29:52 +00003 * Copyright 2020 NXP
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +05304 * Copyright 2016 Freescale Semiconductor, Inc.
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +05305 */
6
7#ifndef __LS1012ARDB_H__
8#define __LS1012ARDB_H__
9
10#include "ls1012a_common.h"
11
Shengzhou Liucb7fb122016-08-26 18:30:39 +080012/* DDR */
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +053013#define CONFIG_DIMM_SLOTS_PER_CTLR 1
14#define CONFIG_CHIP_SELECTS_PER_CTRL 1
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +053015#define CONFIG_SYS_SDRAM_SIZE 0x40000000
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +053016
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +053017/*
18 * I2C IO expander
19 */
20
Yangbo Lu2786f902017-12-08 15:35:35 +080021#define I2C_MUX_IO_ADDR 0x24
Calvin Johnson6e6679b2018-03-08 15:30:30 +053022#define I2C_MUX_IO2_ADDR 0x25
Yangbo Lu2786f902017-12-08 15:35:35 +080023#define I2C_MUX_IO_0 0
24#define I2C_MUX_IO_1 1
25#define SW_BOOT_MASK 0x03
26#define SW_BOOT_EMU 0x02
27#define SW_BOOT_BANK1 0x00
28#define SW_BOOT_BANK2 0x01
29#define SW_REV_MASK 0xF8
30#define SW_REV_A 0xF8
31#define SW_REV_B 0xF0
Yangbo Lu13acb0d2017-12-08 15:35:36 +080032#define SW_REV_C 0xE8
33#define SW_REV_C1 0xE0
34#define SW_REV_C2 0xD8
35#define SW_REV_D 0xD0
36#define SW_REV_E 0xC8
Calvin Johnson6e6679b2018-03-08 15:30:30 +053037#define __PHY_MASK 0xF9
38#define __PHY_ETH2_MASK 0xFB
39#define __PHY_ETH1_MASK 0xFD
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +053040
41/* MMC */
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +053042#ifdef CONFIG_MMC
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +053043#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +053044#endif
45
Prabhakar Kushwahadf21f302016-12-26 12:15:08 +053046
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +053047#define CONFIG_PCIE1 /* PCIE controller 1 */
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +053048
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +053049#define CONFIG_PCI_SCAN_SHOW
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +053050
Rajesh Bhagatd59447a2017-11-30 16:44:38 +053051#undef CONFIG_EXTRA_ENV_SETTINGS
52#define CONFIG_EXTRA_ENV_SETTINGS \
53 "verify=no\0" \
54 "fdt_high=0xffffffffffffffff\0" \
55 "initrd_high=0xffffffffffffffff\0" \
56 "fdt_addr=0x00f00000\0" \
57 "kernel_addr=0x01000000\0" \
Priyanka Singhd06adf22020-01-22 10:29:52 +000058 "kernelheader_addr=0x600000\0" \
Rajesh Bhagatd59447a2017-11-30 16:44:38 +053059 "scriptaddr=0x80000000\0" \
Vinitha Pillai-B572234b56f5b2018-01-09 23:03:42 +053060 "scripthdraddr=0x80080000\0" \
Rajesh Bhagatd59447a2017-11-30 16:44:38 +053061 "fdtheader_addr_r=0x80100000\0" \
62 "kernelheader_addr_r=0x80200000\0" \
Biwen Li5bc151a2020-01-10 17:16:04 +080063 "kernel_addr_r=0x96000000\0" \
Rajesh Bhagatd59447a2017-11-30 16:44:38 +053064 "fdt_addr_r=0x90000000\0" \
65 "load_addr=0xa0000000\0" \
66 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572234b56f5b2018-01-09 23:03:42 +053067 "kernelheader_size=0x40000\0" \
Rajesh Bhagatd59447a2017-11-30 16:44:38 +053068 "console=ttyS0,115200\0" \
69 BOOTENV \
70 "boot_scripts=ls1012ardb_boot.scr\0" \
Vinitha Pillai-B572234b56f5b2018-01-09 23:03:42 +053071 "boot_script_hdr=hdr_ls1012ardb_bs.out\0" \
Rajesh Bhagatd59447a2017-11-30 16:44:38 +053072 "scan_dev_for_boot_part=" \
73 "part list ${devtype} ${devnum} devplist; " \
74 "env exists devplist || setenv devplist 1; " \
75 "for distro_bootpart in ${devplist}; do " \
76 "if fstype ${devtype} " \
77 "${devnum}:${distro_bootpart} " \
78 "bootfstype; then " \
79 "run scan_dev_for_boot; " \
80 "fi; " \
81 "done\0" \
82 "scan_dev_for_boot=" \
83 "echo Scanning ${devtype} " \
84 "${devnum}:${distro_bootpart}...; " \
85 "for prefix in ${boot_prefixes}; do " \
86 "run scan_dev_for_scripts; " \
87 "done;" \
88 "\0" \
Vinitha Pillai-B572234b56f5b2018-01-09 23:03:42 +053089 "boot_a_script=" \
90 "load ${devtype} ${devnum}:${distro_bootpart} " \
91 "${scriptaddr} ${prefix}${script}; " \
92 "env exists secureboot && load ${devtype} " \
93 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai25355ec2019-04-23 05:52:17 +000094 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
95 "env exists secureboot " \
Vinitha Pillai-B572234b56f5b2018-01-09 23:03:42 +053096 "&& esbc_validate ${scripthdraddr};" \
97 "source ${scriptaddr}\0" \
Rajesh Bhagatd59447a2017-11-30 16:44:38 +053098 "installer=load mmc 0:2 $load_addr " \
99 "/flex_installer_arm64.itb; " \
100 "bootm $load_addr#$board\0" \
Biwen Lie7099512019-11-15 15:10:14 +0800101 "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
Rajesh Bhagatd59447a2017-11-30 16:44:38 +0530102 "sf probe && sf read $load_addr " \
Vinitha Pillai-B572234b56f5b2018-01-09 23:03:42 +0530103 "$kernel_addr $kernel_size; env exists secureboot " \
104 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
105 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
106 "bootm $load_addr#$board\0"
Rajesh Bhagatd59447a2017-11-30 16:44:38 +0530107
108#undef CONFIG_BOOTCOMMAND
Rajesh Bhagatfcafef62018-11-05 18:02:53 +0000109#ifdef CONFIG_TFABOOT
110#undef QSPI_NOR_BOOTCOMMAND
111#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
112 "env exists secureboot && esbc_halt;"
113#else
Calvin Johnson0e6101a2018-03-08 15:30:35 +0530114#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
Vinitha Pillai-B572234b56f5b2018-01-09 23:03:42 +0530115 "env exists secureboot && esbc_halt;"
Rajesh Bhagatfcafef62018-11-05 18:02:53 +0000116#endif
Vinitha Pillai-B57223eea4a322017-03-23 13:48:20 +0530117
118#include <asm/fsl_secure_boot.h>
119
Prabhakar Kushwahaa315c662016-06-03 18:41:35 +0530120#endif /* __LS1012ARDB_H__ */