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git01.mediatek.com / filogic / uboot / a727fa0a20f9cc40500023b3d84b6ce390fa1d30 / . / arch / arm / include / asm / arch-npcm8xx / gcr.h
blob: 20230d64e6b29f6dfa4f0addf0c0d411d1967a2f [file] [log] [blame]
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * System Global Control Register definitions
4 * Copyright (c) 2022 Nuvoton Technology Corp.
5 */
6
7#ifndef _NPCM_GCR_H_
8#define _NPCM_GCR_H_
9
10#define NPCM_GCR_BA 0xF0800000
11
12/* On-Chip ARBEL NPCM8XX VERSIONS */
13#define ARBEL_Z1 0x00A35850
14#define ARBEL_A1 0x04a35850
Jim Liuc5cc4bc2023-07-04 16:00:14 +0800[diff] [blame]15#define ARBEL_A2 0x08a35850
Jim Liu147c0002022-09-27 16:45:15 +0800[diff] [blame]16#define ARBEL_NPCM845 0x00000000
17#define ARBEL_NPCM830 0x00300395
18#define ARBEL_NPCM810 0x00000220
19
20#define MFSEL4_ESPISEL BIT(8)
21#define MFSEL1_LPCSEL BIT(26)
22#define INTCR2_WDC BIT(21)
23
24struct npcm_gcr {
25 unsigned int pdid;
26 unsigned int pwron;
27 unsigned int swstrps;
28 unsigned int rsvd1[2];
29 unsigned int miscpe;
30 unsigned int spldcnt;
31 unsigned int rsvd2[1];
32 unsigned int flockr2;
33 unsigned int flockr3;
34 unsigned int rsvd3[3];
35 unsigned int a35_mode;
36 unsigned int spswc;
37 unsigned int intcr;
38 unsigned int intsr;
39 unsigned int obscr1;
40 unsigned int obsdr1;
41 unsigned int rsvd4[1];
42 unsigned int hifcr;
43 unsigned int rsvd5[3];
44 unsigned int intcr2;
45 unsigned int rsvd6[1];
46 unsigned int srcnt;
47 unsigned int ressr;
48 unsigned int rlockr1;
49 unsigned int flockr1;
50 unsigned int dscnt;
51 unsigned int mdlr;
52 unsigned int scrpad_c;
53 unsigned int scrpad_b;
54 unsigned int rsvd7[4];
55 unsigned int daclvlr;
56 unsigned int intcr3;
57 unsigned int pcirctl;
58 unsigned int rsvd8[2];
59 unsigned int vsintr;
60 unsigned int rsvd9[1];
61 unsigned int sd2sur1;
62 unsigned int sd2sur2;
63 unsigned int sd2irv3;
64 unsigned int intcr4;
65 unsigned int obscr2;
66 unsigned int obsdr2;
67 unsigned int rsvd10[5];
68 unsigned int i2csegsel;
69 unsigned int i2csegctl;
70 unsigned int vsrcr;
71 unsigned int mlockr;
72 unsigned int rsvd11[8];
73 unsigned int etsr;
74 unsigned int dft1r;
75 unsigned int dft2r;
76 unsigned int dft3r;
77 unsigned int edffsr;
78 unsigned int rsvd12[1];
79 unsigned int intcrpce3;
80 unsigned int intcrpce2;
81 unsigned int intcrpce0;
82 unsigned int intcrpce1;
83 unsigned int dactest;
84 unsigned int scrpad;
85 unsigned int usb1phyctl;
86 unsigned int usb2phyctl;
87 unsigned int usb3phyctl;
88 unsigned int intsr2;
89 unsigned int intcrpce2b;
90 unsigned int intcrpce0b;
91 unsigned int intcrpce1b;
92 unsigned int intcrpce3b;
93 unsigned int rsvd13[4];
94 unsigned int intcrpce2c;
95 unsigned int intcrpce0c;
96 unsigned int intcrpce1c;
97 unsigned int intcrpce3c;
98 unsigned int rsvd14[40];
99 unsigned int sd2irv4;
100 unsigned int sd2irv5;
101 unsigned int sd2irv6;
102 unsigned int sd2irv7;
103 unsigned int sd2irv8;
104 unsigned int sd2irv9;
105 unsigned int sd2irv10;
106 unsigned int sd2irv11;
107 unsigned int rsvd15[8];
108 unsigned int mfsel1;
109 unsigned int mfsel2;
110 unsigned int mfsel3;
111 unsigned int mfsel4;
112 unsigned int mfsel5;
113 unsigned int mfsel6;
114 unsigned int mfsel7;
115 unsigned int rsvd16[1];
116 unsigned int mfsel_lk1;
117 unsigned int mfsel_lk2;
118 unsigned int mfsel_lk3;
119 unsigned int mfsel_lk4;
120 unsigned int mfsel_lk5;
121 unsigned int mfsel_lk6;
122 unsigned int mfsel_lk7;
123 unsigned int rsvd17[1];
124 unsigned int mfsel_set1;
125 unsigned int mfsel_set2;
126 unsigned int mfsel_set3;
127 unsigned int mfsel_set4;
128 unsigned int mfsel_set5;
129 unsigned int mfsel_set6;
130 unsigned int mfsel_set7;
131 unsigned int rsvd18[1];
132 unsigned int mfsel_clr1;
133 unsigned int mfsel_clr2;
134 unsigned int mfsel_clr3;
135 unsigned int mfsel_clr4;
136 unsigned int mfsel_clr5;
137 unsigned int mfsel_clr6;
138 unsigned int mfsel_clr7;
139 };
140
141#endif