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git01.mediatek.com / filogic / uboot / a70253dc8d1de3e46ab35b59c32db6656ad408ec / . / arch / arm / dts / rk3326-odroid-go2-u-boot.dtsi
blob: a0ab8b69f2e4d09affe5114d157afa16739d9ba0 [file] [log] [blame]
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
4 */
5
Quentin Schulzd9ffa5e2022-09-02 15:10:52 +0200[diff] [blame]6#include "rockchip-u-boot.dtsi"
7
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]8/ {
9 chosen {
10 u-boot,spl-boot-order = &sdmmc;
11 };
Chris Morgana6b6ac22021-08-05 16:27:52 +0800[diff] [blame]12
13 aliases {
14 i2c0 = &i2c0;
15 i2c1 = &i2c1;
16 mmc0 = &sdmmc;
17 serial1 = &uart1;
18 serial2 = &uart2;
19 spi0 = &sfc;
20 };
Chris Morgan09a33b02021-08-25 11:23:57 -0500[diff] [blame]21
Jagan Tekia50c8962021-11-15 23:08:19 +0530[diff] [blame]22 dmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]23 bootph-all;
Jagan Tekia50c8962021-11-15 23:08:19 +0530[diff] [blame]24 compatible = "rockchip,px30-dmc", "syscon";
25 reg = <0x0 0xff2a0000 0x0 0x1000>;
26 };
27
Chris Morgan09a33b02021-08-25 11:23:57 -0500[diff] [blame]28 rng: rng@ff0b0000 {
29 compatible = "rockchip,cryptov2-rng";
30 reg = <0x0 0xff0b0000 0x0 0x4000>;
31 status = "okay";
32 };
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]33};
34
Chris Morganb53667f2021-08-05 11:48:48 -0500[diff] [blame]35/* U-Boot clk driver for px30 cannot set GPU_CLK */
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]36&cru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-all;
Chris Morganb53667f2021-08-05 11:48:48 -0500[diff] [blame]38 assigned-clocks = <&cru PLL_NPLL>,
39 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
40 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
41 <&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>;
42
43 assigned-clock-rates = <1188000000>,
44 <200000000>, <200000000>,
45 <150000000>, <150000000>,
46 <100000000>, <17000000>;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]47};
48
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]49&gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-all;
Jonas Karlman72a54872024-07-25 09:46:03 +0000[diff] [blame]51 gpio-ranges = <&pinctrl 0 0 32>;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]52};
53
54&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-all;
Jonas Karlman72a54872024-07-25 09:46:03 +0000[diff] [blame]56 gpio-ranges = <&pinctrl 0 32 32>;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]57};
58
59&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]60 bootph-all;
Jonas Karlman72a54872024-07-25 09:46:03 +0000[diff] [blame]61 gpio-ranges = <&pinctrl 0 64 32>;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]62};
63
64&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-all;
Jonas Karlman72a54872024-07-25 09:46:03 +0000[diff] [blame]66 gpio-ranges = <&pinctrl 0 96 32>;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]67};
68
69&grf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-all;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]71};
72
73&pmucru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-all;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]75};
76
77&pmugrf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-all;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]79};
80
Quentin Schulz1e9fc7b2024-05-24 11:23:33 +0200[diff] [blame]81&rk817 {
82 regulators {
83 vcc_cam: LDO_REG9 {
84 regulator-name = "vcc_cam";
85 regulator-min-microvolt = <3000000>;
86 regulator-max-microvolt = <3000000>;
87
88 regulator-state-mem {
89 regulator-off-in-suspend;
90 regulator-suspend-microvolt = <3000000>;
91 };
92 };
93 };
94};
95
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]96&saradc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-all;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]98 status = "okay";
99};
100
101&sdmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-all;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]103
104 /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
105 u-boot,spl-fifo-mode;
106};
107
Chris Morgana6b6ac22021-08-05 16:27:52 +0800[diff] [blame]108&sfc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-all;
Chris Morgana6b6ac22021-08-05 16:27:52 +0800[diff] [blame]110};
111
Jagan Teki20759fa2021-11-15 23:08:20 +0530[diff] [blame]112&{/spi@ff3a0000/flash@0} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-all;
Chris Morgana6b6ac22021-08-05 16:27:52 +0800[diff] [blame]114};
115
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]116&uart1 {
117 clock-frequency = <24000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]118 bootph-all;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]119};
120
121&uart2 {
122 clock-frequency = <24000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]123 bootph-all;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]124};
125
126&xin24m {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]127 bootph-all;
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +0200[diff] [blame]128};