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git01.mediatek.com / filogic / uboot / a6b185ecda6ad6fa135262e337aea7348cbee070 / . / arch / arm / dts / stm32mp131.dtsi
blob: 950e172e455f8a9988a0c2a5c2276f02a9cab275 [file] [log] [blame]
Patrick Delaunay8e34fbb2022-05-20 18:24:39 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7
8/ {
9 #address-cells = <1>;
10 #size-cells = <1>;
11
12 cpus {
13 #address-cells = <1>;
14 #size-cells = <0>;
15
16 cpu0: cpu@0 {
17 compatible = "arm,cortex-a7";
18 device_type = "cpu";
19 reg = <0>;
20 };
21 };
22
23 arm-pmu {
24 compatible = "arm,cortex-a7-pmu";
25 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
26 interrupt-affinity = <&cpu0>;
27 interrupt-parent = <&intc>;
28 };
29
30 clocks {
31 clk_axi: clk-axi {
32 #clock-cells = <0>;
33 compatible = "fixed-clock";
34 clock-frequency = <266500000>;
35 };
36
37 clk_hse: clk-hse {
38 #clock-cells = <0>;
39 compatible = "fixed-clock";
40 clock-frequency = <24000000>;
41 };
42
43 clk_hsi: clk-hsi {
44 #clock-cells = <0>;
45 compatible = "fixed-clock";
46 clock-frequency = <64000000>;
47 };
48
49 clk_lsi: clk-lsi {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <32000>;
53 };
54
55 clk_pclk3: clk-pclk3 {
56 #clock-cells = <0>;
57 compatible = "fixed-clock";
58 clock-frequency = <104438965>;
59 };
60
61 clk_pclk4: clk-pclk4 {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 clock-frequency = <133250000>;
65 };
66
67 clk_pll4_p: clk-pll4_p {
68 #clock-cells = <0>;
69 compatible = "fixed-clock";
70 clock-frequency = <50000000>;
71 };
72
73 clk_pll4_r: clk-pll4_r {
74 #clock-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <99000000>;
77 };
78 };
79
80 intc: interrupt-controller@a0021000 {
81 compatible = "arm,cortex-a7-gic";
82 #interrupt-cells = <3>;
83 interrupt-controller;
84 reg = <0xa0021000 0x1000>,
85 <0xa0022000 0x2000>;
86 };
87
88 psci {
89 compatible = "arm,psci-1.0";
90 method = "smc";
91 };
92
93 timer {
94 compatible = "arm,armv7-timer";
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
96 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
97 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
98 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
99 interrupt-parent = <&intc>;
100 always-on;
101 };
102
103 soc {
104 compatible = "simple-bus";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 interrupt-parent = <&intc>;
108 ranges;
109
110 uart4: serial@40010000 {
111 compatible = "st,stm32h7-uart";
112 reg = <0x40010000 0x400>;
113 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&clk_hsi>;
115 status = "disabled";
116 };
117
118 dma1: dma-controller@48000000 {
119 compatible = "st,stm32-dma";
120 reg = <0x48000000 0x400>;
121 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&clk_pclk4>;
130 #dma-cells = <4>;
131 st,mem2mem;
132 dma-requests = <8>;
133 };
134
135 dma2: dma-controller@48001000 {
136 compatible = "st,stm32-dma";
137 reg = <0x48001000 0x400>;
138 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&clk_pclk4>;
147 #dma-cells = <4>;
148 st,mem2mem;
149 dma-requests = <8>;
150 };
151
152 dmamux1: dma-router@48002000 {
153 compatible = "st,stm32h7-dmamux";
154 reg = <0x48002000 0x40>;
155 clocks = <&clk_pclk4>;
156 #dma-cells = <3>;
157 dma-masters = <&dma1 &dma2>;
158 dma-requests = <128>;
159 dma-channels = <16>;
160 };
161
162 exti: interrupt-controller@5000d000 {
163 compatible = "st,stm32mp13-exti", "syscon";
164 interrupt-controller;
165 #interrupt-cells = <2>;
166 reg = <0x5000d000 0x400>;
167 };
168
169 syscfg: syscon@50020000 {
170 compatible = "st,stm32mp157-syscfg", "syscon";
171 reg = <0x50020000 0x400>;
172 clocks = <&clk_pclk3>;
173 };
174
175 mdma: dma-controller@58000000 {
176 compatible = "st,stm32h7-mdma";
177 reg = <0x58000000 0x1000>;
178 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&clk_pclk4>;
180 #dma-cells = <5>;
181 dma-channels = <32>;
182 dma-requests = <48>;
183 };
184
185 sdmmc1: mmc@58005000 {
186 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
187 arm,primecell-periphid = <0x20253180>;
188 reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
189 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
190 interrupt-names = "cmd_irq";
191 clocks = <&clk_pll4_p>;
192 clock-names = "apb_pclk";
193 cap-sd-highspeed;
194 cap-mmc-highspeed;
195 max-frequency = <130000000>;
196 status = "disabled";
197 };
198
199 sdmmc2: mmc@58007000 {
200 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
201 arm,primecell-periphid = <0x20253180>;
202 reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
203 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
204 interrupt-names = "cmd_irq";
205 clocks = <&clk_pll4_p>;
206 clock-names = "apb_pclk";
207 cap-sd-highspeed;
208 cap-mmc-highspeed;
209 max-frequency = <130000000>;
210 status = "disabled";
211 };
212
213 iwdg2: watchdog@5a002000 {
214 compatible = "st,stm32mp1-iwdg";
215 reg = <0x5a002000 0x400>;
216 clocks = <&clk_pclk4>, <&clk_lsi>;
217 clock-names = "pclk", "lsi";
218 status = "disabled";
219 };
220
221 bsec: efuse@5c005000 {
222 compatible = "st,stm32mp13-bsec";
223 reg = <0x5c005000 0x400>;
224 #address-cells = <1>;
225 #size-cells = <1>;
226
227 part_number_otp: part_number_otp@4 {
228 reg = <0x4 0x2>;
229 };
230 ts_cal1: calib@5c {
231 reg = <0x5c 0x2>;
232 };
233 ts_cal2: calib@5e {
234 reg = <0x5e 0x2>;
235 };
236 };
237
238 /*
239 * Break node order to solve dependency probe issue between
240 * pinctrl and exti.
241 */
242 pinctrl: pin-controller@50002000 {
243 #address-cells = <1>;
244 #size-cells = <1>;
245 compatible = "st,stm32mp135-pinctrl";
246 ranges = <0 0x50002000 0x8400>;
247 pins-are-numbered;
248
249 gpioa: gpio@50002000 {
250 gpio-controller;
251 #gpio-cells = <2>;
252 interrupt-controller;
253 #interrupt-cells = <2>;
254 reg = <0x0 0x400>;
255 clocks = <&clk_pclk4>;
256 st,bank-name = "GPIOA";
257 ngpios = <16>;
258 gpio-ranges = <&pinctrl 0 0 16>;
259 };
260
261 gpiob: gpio@50003000 {
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
266 reg = <0x1000 0x400>;
267 clocks = <&clk_pclk4>;
268 st,bank-name = "GPIOB";
269 ngpios = <16>;
270 gpio-ranges = <&pinctrl 0 16 16>;
271 };
272
273 gpioc: gpio@50004000 {
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
278 reg = <0x2000 0x400>;
279 clocks = <&clk_pclk4>;
280 st,bank-name = "GPIOC";
281 ngpios = <16>;
282 gpio-ranges = <&pinctrl 0 32 16>;
283 };
284
285 gpiod: gpio@50005000 {
286 gpio-controller;
287 #gpio-cells = <2>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 reg = <0x3000 0x400>;
291 clocks = <&clk_pclk4>;
292 st,bank-name = "GPIOD";
293 ngpios = <16>;
294 gpio-ranges = <&pinctrl 0 48 16>;
295 };
296
297 gpioe: gpio@50006000 {
298 gpio-controller;
299 #gpio-cells = <2>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 reg = <0x4000 0x400>;
303 clocks = <&clk_pclk4>;
304 st,bank-name = "GPIOE";
305 ngpios = <16>;
306 gpio-ranges = <&pinctrl 0 64 16>;
307 };
308
309 gpiof: gpio@50007000 {
310 gpio-controller;
311 #gpio-cells = <2>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 reg = <0x5000 0x400>;
315 clocks = <&clk_pclk4>;
316 st,bank-name = "GPIOF";
317 ngpios = <16>;
318 gpio-ranges = <&pinctrl 0 80 16>;
319 };
320
321 gpiog: gpio@50008000 {
322 gpio-controller;
323 #gpio-cells = <2>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
326 reg = <0x6000 0x400>;
327 clocks = <&clk_pclk4>;
328 st,bank-name = "GPIOG";
329 ngpios = <16>;
330 gpio-ranges = <&pinctrl 0 96 16>;
331 };
332
333 gpioh: gpio@50009000 {
334 gpio-controller;
335 #gpio-cells = <2>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 reg = <0x7000 0x400>;
339 clocks = <&clk_pclk4>;
340 st,bank-name = "GPIOH";
341 ngpios = <15>;
342 gpio-ranges = <&pinctrl 0 112 15>;
343 };
344
345 gpioi: gpio@5000a000 {
346 gpio-controller;
347 #gpio-cells = <2>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 reg = <0x8000 0x400>;
351 clocks = <&clk_pclk4>;
352 st,bank-name = "GPIOI";
353 ngpios = <8>;
354 gpio-ranges = <&pinctrl 0 128 8>;
355 };
356 };
357 };
358};