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git01.mediatek.com / filogic / uboot / a6b185ecda6ad6fa135262e337aea7348cbee070 / . / arch / arm / dts / imx8mp-verdin.dts
blob: bc8bf4dad56b45b806a9a9d4db674f0447a41e0c [file] [log] [blame]
Marcel Ziswiler36a439d2022-02-07 11:54:13 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/usb/pd.h>
9#include "imx8mp.dtsi"
10
11/ {
12 model = "Toradex Verdin iMX8M Plus";
13 compatible = "toradex,verdin-imx8mp", "fsl,imx8mp";
14
15 aliases {
16 eeprom0 = &eeprom_module;
17 eeprom1 = &eeprom_carrier;
18 eeprom2 = &eeprom_mipi_dsi;
19 /* Ethernet aliases to ensure correct MAC addresses */
20 ethernet0 = &eqos;
21 ethernet1 = &fec;
22 };
23
24 chosen {
25 bootargs = "console=ttymxc2,115200 earlycon";
26 stdout-path = &uart3;
27 };
28
29 reg_usb1_host_vbus: regulator-usb1-vbus {
30 compatible = "regulator-fixed";
31 enable-active-high;
32 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; /* USB_2_EN */
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_usb1_vbus>;
35 regulator-always-on;
36 regulator-max-microvolt = <5000000>;
37 regulator-min-microvolt = <5000000>;
38 regulator-name = "usb1_host_vbus";
39 };
40
41 reg_usdhc2_vmmc: regulator-usdhc2 {
42 compatible = "regulator-fixed";
43 enable-active-high;
44 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; /* SD_1_PWR_EN */
45 off-on-delay-us = <12000>;
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
48 regulator-max-microvolt = <3300000>;
49 regulator-min-microvolt = <3300000>;
50 regulator-name = "V3.3_SD";
51 startup-delay-us = <100>;
52 };
53};
54
55&eqos {
56 phy-handle = <&ethphy0>;
57 phy-mode = "rgmii-id";
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_eqos>;
60 status = "okay";
61
62 mdio {
63 compatible = "snps,dwmac-mdio";
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 ethphy0: ethernet-phy@7 {
68 compatible = "ethernet-phy-ieee802.3-c22";
69 reg = <7>;
70 };
71 };
72};
73
74&fec {
75 fsl,magic-packet;
76 phy-handle = <&ethphy1>;
77 phy-mode = "rgmii-id";
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_fec>;
80
81 status = "okay";
82
83 mdio {
84 #address-cells = <1>;
85 #size-cells = <0>;
86
87 ethphy1: ethernet-phy@7 {
88 compatible = "ethernet-phy-ieee802.3-c22";
89 reg = <7>;
90 };
91 };
92};
93
94&gpio2 {
95 regulator-ethphy {
96 gpio-hog;
97 gpios = <20 GPIO_ACTIVE_HIGH>;
98 line-name = "reg_ethphy";
99 output-high;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_reg_eth>;
102 };
103
104 ctrl_sleep_moci {
105 gpio-hog;
106 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
107 gpios = <29 GPIO_ACTIVE_HIGH>;
108 line-name = "CTRL_SLEEP_MOCI#";
109 output-high;
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
112 };
113};
114
115/* Verdin PMIC_I2C */
116&i2c1 {
117 clock-frequency = <400000>;
118 pinctrl-names = "default", "gpio";
119 pinctrl-0 = <&pinctrl_i2c1>;
120 pinctrl-1 = <&pinctrl_i2c1_gpio>;
121 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
122 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
123 status = "okay";
124
125 pmic: pca9450@25 {
126 compatible = "nxp,pca9450c";
127 reg = <0x25>;
128 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
129
130 regulators {
131 #address-cells = <1>;
132 /* Run/Standby voltage */
133 pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
134 pca9450,pmic-buck2-uses-i2c-dvs;
135 #size-cells = <0>;
136
137 buck1_reg: regulator@0 {
138 reg = <0>;
139 regulator-always-on;
140 regulator-boot-on;
141 regulator-compatible = "buck1";
142 regulator-max-microvolt = <2187500>;
143 regulator-min-microvolt = <600000>;
144 regulator-ramp-delay = <3125>;
145 };
146
147 buck2_reg: regulator@1 {
148 reg = <1>;
149 regulator-always-on;
150 regulator-boot-on;
151 regulator-compatible = "buck2";
152 regulator-max-microvolt = <2187500>;
153 regulator-min-microvolt = <600000>;
154 regulator-ramp-delay = <3125>;
155 };
156
157 buck4_reg: regulator@3 {
158 reg = <3>;
159 regulator-always-on;
160 regulator-boot-on;
161 regulator-compatible = "buck4";
162 regulator-max-microvolt = <3400000>;
163 regulator-min-microvolt = <600000>;
164 };
165
166 buck5_reg: regulator@4 {
167 reg = <4>;
168 regulator-always-on;
169 regulator-boot-on;
170 regulator-compatible = "buck5";
171 regulator-max-microvolt = <3400000>;
172 regulator-min-microvolt = <600000>;
173 };
174
175 buck6_reg: regulator@5 {
176 reg = <5>;
177 regulator-always-on;
178 regulator-boot-on;
179 regulator-compatible = "buck6";
180 regulator-max-microvolt = <3400000>;
181 regulator-min-microvolt = <600000>;
182 };
183
184 ldo1_reg: regulator@6 {
185 reg = <6>;
186 regulator-always-on;
187 regulator-boot-on;
188 regulator-compatible = "ldo1";
189 regulator-max-microvolt = <3300000>;
190 regulator-min-microvolt = <1600000>;
191 };
192
193 ldo2_reg: regulator@7 {
194 reg = <7>;
195 regulator-always-on;
196 regulator-boot-on;
197 regulator-compatible = "ldo2";
198 regulator-max-microvolt = <1150000>;
199 regulator-min-microvolt = <800000>;
200 };
201
202 ldo3_reg: regulator@8 {
203 reg = <8>;
204 regulator-always-on;
205 regulator-boot-on;
206 regulator-compatible = "ldo3";
207 regulator-max-microvolt = <3300000>;
208 regulator-min-microvolt = <800000>;
209 };
210
211 ldo4_reg: regulator@9 {
212 reg = <9>;
213 regulator-always-on;
214 regulator-boot-on;
215 regulator-compatible = "ldo4";
216 regulator-max-microvolt = <3300000>;
217 regulator-min-microvolt = <800000>;
218 };
219
220 ldo5_reg: regulator@10 { /* +V3.3_1.8_SD */
221 reg = <10>;
222 regulator-compatible = "ldo5";
223 regulator-max-microvolt = <3300000>;
224 regulator-min-microvolt = <1800000>;
225 };
226 };
227 };
228
229 /* Epson RX8130 real time clock on carrier board */
230 rtc: rx8130@32 {
231 compatible = "epson,rx8130";
232 reg = <0x32>;
233 };
234
235 eeprom_module: eeprom@50 {
236 compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
237 pagesize = <16>;
238 reg = <0x50>;
239 };
240};
241
242/* Verdin I2C2 DSI */
243&i2c2 {
244 clock-frequency = <400000>;
245 pinctrl-names = "default", "gpio";
246 pinctrl-0 = <&pinctrl_i2c2>;
247 pinctrl-1 = <&pinctrl_i2c2_gpio>;
248 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
249 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
250 status = "okay";
251};
252
253/* Verdin I2C4 CSI */
254&i2c3 {
255 clock-frequency = <100000>;
256 pinctrl-names = "default", "gpio";
257 pinctrl-0 = <&pinctrl_i2c3>;
258 pinctrl-1 = <&pinctrl_i2c3_gpio>;
259 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
260 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
261 status = "okay";
262
263 pca6416: gpio@20 {
264 compatible = "ti,tca6416";
265 #gpio-cells = <2>;
266 gpio-controller;
267 reg = <0x20>;
268 };
269};
270
271/* Verdin I2C1 */
272&i2c4 {
273 clock-frequency = <100000>;
274 pinctrl-names = "default", "gpio";
275 pinctrl-0 = <&pinctrl_i2c4>;
276 pinctrl-1 = <&pinctrl_i2c4_gpio>;
277 scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
278 sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
279 status = "okay";
280
281 /* EEPROM on MIPI-DSI to HDMI adapter */
282 eeprom_mipi_dsi: eeprom@50 {
283 compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
284 pagesize = <16>;
285 reg = <0x50>;
286 };
287
288 /* EEPROM on Verdin Development board */
289 eeprom_carrier: eeprom@57 {
290 compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
291 pagesize = <16>;
292 reg = <0x57>;
293 };
294};
295
296&snvs_pwrkey {
297 status = "okay";
298};
299
300/* Verdin UART3 */
301&uart3 {
302 /* console */
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_uart3>;
305 status = "okay";
306};
307
308&usb3_phy0 {
309 status = "okay";
310};
311
312&usb_dwc3_0 {
313 adp-disable;
314 dr_mode = "otg";
315 hnp-disable;
316 srp-disable;
317 usb-role-switch;
318 status = "okay";
319};
320
321&usb3_phy1 {
322 status = "okay";
323};
324
325&usb_dwc3_1 {
326 dr_mode = "host";
327 status = "okay";
328};
329
330/* Verdin SDIO 1 */
331&usdhc2 {
332 bus-width = <4>;
333 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
334 pinctrl-names = "default", "state_100mhz", "state_200mhz";
335 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
336 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
337 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
338 vmmc-supply = <&reg_usdhc2_vmmc>;
339 status = "okay";
340};
341
342/* On-module eMMC */
343&usdhc3 {
344 bus-width = <8>;
345 non-removable;
346 pinctrl-names = "default", "state_100mhz", "state_200mhz";
347 pinctrl-0 = <&pinctrl_usdhc3>;
348 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
349 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
350 status = "okay";
351};
352
353&wdog1 {
354 fsl,ext-reset-output;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_wdog>;
357 status = "okay";
358};
359
360&iomuxc {
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, <&pinctrl_gpio3>,
363 <&pinctrl_gpio4>, <&pinctrl_gpio5>, <&pinctrl_gpio6>,
364 <&pinctrl_gpio7>, <&pinctrl_gpio8>;
365
366 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
367 fsl,pins = <
368 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4 /* SODIMM 256 */
369 >;
370 };
371
372 pinctrl_eqos: eqosgrp {
373 fsl,pins = <
374 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
375 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
376 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
377 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
378 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
379 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
380 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
381 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
382 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
383 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
384 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
385 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
386 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
387 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
388 >;
389 };
390
391 pinctrl_fec: fecgrp {
392 fsl,pins = <
393 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
394 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
395 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
396 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
397 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
398 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
399 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
400 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
401 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
402 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
403 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
404 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
405 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
406 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
407 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
408 >;
409 };
410
411 /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */
412 pinctrl_gpio1: gpio1grp {
413 fsl,pins = <
414 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184 /* SODIMM 206 */
415 >;
416 };
417
418 pinctrl_gpio2: gpio2grp {
419 fsl,pins = <
420 MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x184 /* SODIMM 208 */
421 >;
422 };
423
424 pinctrl_gpio3: gpio3grp {
425 fsl,pins = <
426 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184 /* SODIMM 210 */
427 >;
428 };
429
430 pinctrl_gpio4: gpio4grp {
431 fsl,pins = <
432 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184 /* SODIMM 212 */
433 >;
434 };
435
436 pinctrl_gpio5: gpio5grp {
437 fsl,pins = <
438 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184 /* SODIMM 216 */
439 >;
440 };
441
442 pinctrl_gpio6: gpio6grp {
443 fsl,pins = <
444 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184 /* SODIMM 218 */
445 >;
446 };
447
448 pinctrl_gpio7: gpio7grp {
449 fsl,pins = <
450 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184 /* SODIMM 220 */
451 >;
452 };
453
454 pinctrl_gpio8: gpio8grp {
455 fsl,pins = <
456 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184 /* SODIMM 222 */
457 >;
458 };
459
460 pinctrl_i2c1: i2c1grp {
461 fsl,pins = <
462 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
463 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
464 >;
465 };
466
467 pinctrl_i2c2: i2c2grp {
468 fsl,pins = <
469 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
470 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
471 >;
472 };
473
474 pinctrl_i2c3: i2c3grp {
475 fsl,pins = <
476 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
477 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
478 >;
479 };
480
481 pinctrl_i2c4: i2c4grp {
482 fsl,pins = <
483 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
484 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
485 >;
486 };
487
488 pinctrl_i2c1_gpio: i2c1grp-gpio {
489 fsl,pins = <
490 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
491 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
492 >;
493 };
494
495 pinctrl_i2c2_gpio: i2c2grp-gpio {
496 fsl,pins = <
497 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
498 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
499 >;
500 };
501
502 pinctrl_i2c3_gpio: i2c3grp-gpio {
503 fsl,pins = <
504 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
505 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
506 >;
507 };
508
509 pinctrl_i2c4_gpio: i2c4grp-gpio {
510 fsl,pins = <
511 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
512 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
513 >;
514 };
515
516 pinctrl_reg_eth: regethgrp {
517 fsl,pins = <
518 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184
519 >;
520 };
521
522 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
523 fsl,pins = <
524 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x41
525 >;
526 };
527
528 pinctrl_uart3: uart3grp {
529 fsl,pins = <
530 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
531 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
532 >;
533 };
534
535 pinctrl_usb1_vbus: usb1grp {
536 fsl,pins = <
537 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
538 >;
539 };
540
541 pinctrl_usdhc2: usdhc2grp {
542 fsl,pins = <
543 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
544 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
545 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
546 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
547 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
548 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
549 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
550 >;
551 };
552
553 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
554 fsl,pins = <
555 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
556 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
557 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
558 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
559 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
560 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
561 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
562 >;
563 };
564
565 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
566 fsl,pins = <
567 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
568 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
569 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
570 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
571 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
572 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
573 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
574 >;
575 };
576
577 pinctrl_usdhc2_gpio: usdhc2grp-gpio {
578 fsl,pins = <
579 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
580 >;
581 };
582
583 pinctrl_usdhc3: usdhc3grp {
584 fsl,pins = <
585 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
586 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
587 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
588 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
589 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
590 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
591 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
592 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
593 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
594 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
595 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
596 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
597 >;
598 };
599
600 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
601 fsl,pins = <
602 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
603 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
604 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
605 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
606 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
607 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
608 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
609 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
610 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
611 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
612 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
613 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
614 >;
615 };
616
617 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
618 fsl,pins = <
619 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
620 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
621 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
622 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
623 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
624 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
625 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
626 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
627 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
628 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
629 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
630 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
631 >;
632 };
633
634 pinctrl_wdog: wdoggrp {
635 fsl,pins = <
636 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
637 >;
638 };
639};