wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Texas Instruments. |
| 4 | * Kshitij Gupta <kshitij@ti.com> |
| 5 | * Configuation settings for the TI OMAP Innovator board. |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #ifndef __CONFIG_H |
| 27 | #define __CONFIG_H |
| 28 | |
| 29 | /* |
| 30 | * High Level Configuration Options |
| 31 | * (easy to change) |
| 32 | */ |
| 33 | #define CONFIG_ARM925T 1 /* This is an arm925t CPU */ |
| 34 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
| 35 | #define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ |
| 36 | #define CONFIG_INNOVATOROMAP1510 1 /* a Innovator Board */ |
| 37 | |
| 38 | /* input clock of PLL */ |
| 39 | #define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */ |
| 40 | |
| 41 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
| 42 | |
| 43 | #define CONFIG_MISC_INIT_R |
| 44 | |
| 45 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
| 46 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
wdenk | 8676590 | 2003-12-06 23:55:10 +0000 | [diff] [blame] | 47 | #define CONFIG_INITRD_TAG 1 |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 48 | |
| 49 | /* |
| 50 | * Size of malloc() pool |
| 51 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 53 | |
| 54 | /* |
| 55 | * Hardware drivers |
| 56 | */ |
| 57 | /* |
| 58 | #define CONFIG_DRIVER_SMC9196 |
| 59 | #define CONFIG_SMC9196_BASE 0x08000300 |
| 60 | #define CONFIG_SMC9196_EXT_PHY |
| 61 | */ |
Nishanth Menon | ee1c20f | 2009-10-16 00:06:37 -0500 | [diff] [blame] | 62 | #define CONFIG_LAN91C96 |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 63 | #define CONFIG_LAN91C96_BASE 0x08000300 |
| 64 | #define CONFIG_LAN91C96_EXT_PHY |
| 65 | |
| 66 | /* |
| 67 | * NS16550 Configuration |
| 68 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 69 | #define CONFIG_SYS_NS16550 |
| 70 | #define CONFIG_SYS_NS16550_SERIAL |
| 71 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 72 | #define CONFIG_SYS_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ |
| 73 | #define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 74 | |
| 75 | /* |
| 76 | * select serial console configuration |
| 77 | */ |
| 78 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1510 Innovator */ |
| 79 | |
| 80 | /* allow to overwrite serial and ethaddr */ |
| 81 | #define CONFIG_ENV_OVERWRITE |
| 82 | |
| 83 | #define CONFIG_ENV_OVERWRITE |
| 84 | #define CONFIG_CONS_INDEX 1 |
| 85 | #define CONFIG_BAUDRATE 115200 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 86 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 87 | |
Jon Loeliger | 4bd7e1b | 2007-07-04 22:33:13 -0500 | [diff] [blame] | 88 | |
| 89 | /* |
| 90 | * Command line configuration. |
| 91 | */ |
| 92 | #include <config_cmd_default.h> |
| 93 | |
| 94 | #define CONFIG_CMD_DHCP |
| 95 | |
| 96 | |
Jon Loeliger | c6d535a | 2007-07-09 21:57:31 -0500 | [diff] [blame] | 97 | /* |
| 98 | * BOOTP options |
| 99 | */ |
| 100 | #define CONFIG_BOOTP_SUBNETMASK |
| 101 | #define CONFIG_BOOTP_GATEWAY |
| 102 | #define CONFIG_BOOTP_HOSTNAME |
| 103 | #define CONFIG_BOOTP_BOOTPATH |
| 104 | |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 105 | |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 106 | #include <configs/omap1510.h> |
| 107 | |
| 108 | #define CONFIG_BOOTDELAY 3 |
wdenk | 8676590 | 2003-12-06 23:55:10 +0000 | [diff] [blame] | 109 | #define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp" |
| 110 | #define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | #define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 112 | |
Jon Loeliger | 4bd7e1b | 2007-07-04 22:33:13 -0500 | [diff] [blame] | 113 | #if defined(CONFIG_CMD_KGDB) |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 114 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
| 115 | /* what's this ? it's not used anywhere */ |
| 116 | #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
| 117 | #endif |
| 118 | |
| 119 | /* |
| 120 | * Miscellaneous configurable options |
| 121 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 122 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 123 | #define CONFIG_SYS_PROMPT "OMAP1510 Innovator # " /* Monitor Command Prompt */ |
| 124 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 125 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 126 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 127 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 128 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 129 | #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ |
| 130 | #define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 131 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 132 | #define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 133 | |
Ladislav Michl | a16482e | 2009-04-22 01:12:04 +0200 | [diff] [blame] | 134 | /* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1. |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 135 | * This time is further subdivided by a local divisor. |
| 136 | */ |
Ladislav Michl | 993e57d | 2009-03-30 18:58:41 +0200 | [diff] [blame] | 137 | #define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */ |
Ladislav Michl | a16482e | 2009-04-22 01:12:04 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
| 139 | #define CONFIG_SYS_HZ 1000 |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 140 | |
| 141 | /*----------------------------------------------------------------------- |
| 142 | * Stack sizes |
| 143 | * |
| 144 | * The stack sizes are set up in start.S using the settings below |
| 145 | */ |
| 146 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
| 147 | #ifdef CONFIG_USE_IRQ |
| 148 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
| 149 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
| 150 | #endif |
| 151 | |
| 152 | /*----------------------------------------------------------------------- |
| 153 | * Physical Memory Map |
| 154 | */ |
| 155 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
| 156 | #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
| 157 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
| 158 | |
| 159 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
| 160 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 161 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 162 | |
Aneesh V | 24e0a58 | 2011-06-09 08:54:51 -0400 | [diff] [blame] | 163 | #define PHYS_SRAM 0x20000000 |
| 164 | |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 165 | /*----------------------------------------------------------------------- |
| 166 | * FLASH and environment organization |
| 167 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 168 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 169 | #define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ |
wdenk | e85b7a5 | 2004-10-10 22:16:06 +0000 | [diff] [blame] | 170 | #define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 171 | #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ |
| 172 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) |
| 173 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ |
| 174 | #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ |
| 175 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE } |
wdenk | e85b7a5 | 2004-10-10 22:16:06 +0000 | [diff] [blame] | 176 | |
| 177 | /*----------------------------------------------------------------------- |
| 178 | * FLASH driver setup |
| 179 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 180 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 181 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 182 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ |
| 183 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 184 | |
| 185 | /* timeout values are in ticks */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 186 | #define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
| 187 | #define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 188 | |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 189 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 190 | #define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ |
| 191 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | #define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 193 | |
Aneesh V | 24e0a58 | 2011-06-09 08:54:51 -0400 | [diff] [blame] | 194 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 195 | #define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM |
| 196 | |
wdenk | f6f96f7 | 2003-07-15 20:04:06 +0000 | [diff] [blame] | 197 | #endif /* __CONFIG_H */ |