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Stefan Roesea34997d2005-09-22 09:16:57 +02001/*
2 * (C) Copyright 2005
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesea34997d2005-09-22 09:16:57 +02006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405GP 1 /* This is a PPC405 CPU */
Stefan Roesea34997d2005-09-22 09:16:57 +020021
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020022#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
Matthias Fuchs080763f2015-01-12 22:47:32 +010023#define CONFIG_DISPLAY_BOARDINFO
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020024
Stefan Roesea34997d2005-09-22 09:16:57 +020025#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
26
27#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
28
29#define CONFIG_BAUDRATE 9600
30#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
31
32#undef CONFIG_BOOTARGS
33#undef CONFIG_BOOTCOMMAND
34
35#define CONFIG_PREBOOT /* enable preboot variable */
36
37#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020038#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roesea34997d2005-09-22 09:16:57 +020039
40#define CONFIG_MII 1 /* MII PHY management */
41#define CONFIG_PHY_ADDR 0 /* PHY address */
42
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050043/*
Jon Loeligerf5709d12007-07-10 09:02:57 -050044 * BOOTP options
45 */
46#define CONFIG_BOOTP_BOOTFILESIZE
47#define CONFIG_BOOTP_BOOTPATH
48#define CONFIG_BOOTP_GATEWAY
49#define CONFIG_BOOTP_HOSTNAME
50
51
52/*
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050053 * Command line configuration.
54 */
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050055#define CONFIG_CMD_PCI
56#define CONFIG_CMD_IRQ
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050057#define CONFIG_CMD_I2C
58#define CONFIG_CMD_BSP
59#define CONFIG_CMD_EEPROM
60
Stefan Roesea34997d2005-09-22 09:16:57 +020061
62#undef CONFIG_WATCHDOG /* watchdog disabled */
63
64#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
65
66/*
67 * Miscellaneous configurable options
68 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020069#define CONFIG_SYS_LONGHELP /* undef to save memory */
Stefan Roesea34997d2005-09-22 09:16:57 +020070
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Stefan Roesea34997d2005-09-22 09:16:57 +020072
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050073#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roesea34997d2005-09-22 09:16:57 +020075#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roesea34997d2005-09-22 09:16:57 +020077#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020078#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
79#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
80#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roesea34997d2005-09-22 09:16:57 +020081
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
Stefan Roesea34997d2005-09-22 09:16:57 +020083
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
Stefan Roesea34997d2005-09-22 09:16:57 +020085
86#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
87
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
89#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roesea34997d2005-09-22 09:16:57 +020090
Stefan Roese3ddce572010-09-20 16:05:31 +020091#define CONFIG_CONS_INDEX 2 /* Use UART1 */
Stefan Roese3ddce572010-09-20 16:05:31 +020092#define CONFIG_SYS_NS16550_SERIAL
93#define CONFIG_SYS_NS16550_REG_SIZE 1
94#define CONFIG_SYS_NS16550_CLK get_serial_clock()
95
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020097#define CONFIG_SYS_BASE_BAUD 691200
Stefan Roesea34997d2005-09-22 09:16:57 +020098
99/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roesea34997d2005-09-22 09:16:57 +0200101 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
102 57600, 115200, 230400, 460800, 921600 }
103
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
105#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roesea34997d2005-09-22 09:16:57 +0200106
Stefan Roesea34997d2005-09-22 09:16:57 +0200107#define CONFIG_LOOPW 1 /* enable loopw command */
108
109#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
110
111#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
112
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200113#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
Stefan Roesea34997d2005-09-22 09:16:57 +0200114
115/*-----------------------------------------------------------------------
116 * PCI stuff
117 *-----------------------------------------------------------------------
118 */
119#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
120#define PCI_HOST_FORCE 1 /* configure as pci host */
121#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
122
123#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +0000124#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roesea34997d2005-09-22 09:16:57 +0200125#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
126#define CONFIG_PCI_PNP /* do pci plug-and-play */
127 /* resource configuration */
128
129#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
130
131#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
132
133#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
134
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
136#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */
137#define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
Stefan Roese1c671a92006-01-18 20:03:15 +0100138
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200139#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
140#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
141#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
142#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */
143#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
144#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
Stefan Roesea34997d2005-09-22 09:16:57 +0200145
146/*-----------------------------------------------------------------------
147 * Start addresses for the final memory configuration
148 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Stefan Roesea34997d2005-09-22 09:16:57 +0200150 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#define CONFIG_SYS_SDRAM_BASE 0x00000000
152#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
153#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
154#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
155#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
Stefan Roesea34997d2005-09-22 09:16:57 +0200156
157/*
158 * For booting Linux, the board info and command line data
159 * have to be in the first 8 MB of memory, since this is
160 * the maximum mapped by the Linux kernel during initialization.
161 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200162#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roesea34997d2005-09-22 09:16:57 +0200163/*-----------------------------------------------------------------------
164 * FLASH organization
165 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200166#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
167#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Stefan Roesea34997d2005-09-22 09:16:57 +0200168
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200169#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
170#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roesea34997d2005-09-22 09:16:57 +0200171
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
173#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
174#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
Stefan Roesea34997d2005-09-22 09:16:57 +0200175
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
177#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
178#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
Stefan Roesea34997d2005-09-22 09:16:57 +0200179
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roesea34997d2005-09-22 09:16:57 +0200181
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200182#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200183#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
184#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
Stefan Roesea34997d2005-09-22 09:16:57 +0200185
186/*-----------------------------------------------------------------------
187 * I2C EEPROM (CAT24WC16) for environment
188 */
Dirk Eibach42b204f2013-04-25 02:40:01 +0000189#define CONFIG_SYS_I2C
190#define CONFIG_SYS_I2C_PPC4XX
191#define CONFIG_SYS_I2C_PPC4XX_CH0
192#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
193#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Stefan Roesea34997d2005-09-22 09:16:57 +0200194
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
196#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roesea34997d2005-09-22 09:16:57 +0200197/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200198#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
199#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
Stefan Roesea34997d2005-09-22 09:16:57 +0200200 /* 16 byte page write mode using*/
201 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Stefan Roesea34997d2005-09-22 09:16:57 +0200203
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204#define CONFIG_SYS_EEPROM_WREN 1
Stefan Roesea34997d2005-09-22 09:16:57 +0200205
Stefan Roesea34997d2005-09-22 09:16:57 +0200206/*
207 * Init Memory Controller:
208 *
209 * BR0/1 and OR0/1 (FLASH)
210 */
211#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
212#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
213
214/*-----------------------------------------------------------------------
215 * External Bus Controller (EBC) Setup
216 */
217
218/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200219#define CONFIG_SYS_EBC_PB0AP 0x92015480
220#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
Stefan Roesea34997d2005-09-22 09:16:57 +0200221
222/* Memory Bank 2 (PB0) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200223#define CONFIG_SYS_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
224#define CONFIG_SYS_EBC_PB2CR 0xEF018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
Stefan Roesea34997d2005-09-22 09:16:57 +0200225
226/* Memory Bank 3 (PB1) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200227#define CONFIG_SYS_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
228#define CONFIG_SYS_EBC_PB3CR 0xEF118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
Stefan Roesea34997d2005-09-22 09:16:57 +0200229
230/*-----------------------------------------------------------------------
231 * Definitions for initial stack pointer and data area (in data cache)
232 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200233#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
Stefan Roesea34997d2005-09-22 09:16:57 +0200234
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200235#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200236#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200237#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roesea34997d2005-09-22 09:16:57 +0200239
240/*-----------------------------------------------------------------------
241 * GPIO definitions
242 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200243#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */
244#define CONFIG_SYS_SELF_RST (0x80000000 >> 14) /* GPIO14 */
245#define CONFIG_SYS_PB_LED (0x80000000 >> 16) /* GPIO16 */
246#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */
Stefan Roesea34997d2005-09-22 09:16:57 +0200247
Stefan Roesea34997d2005-09-22 09:16:57 +0200248#endif /* __CONFIG_H */