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Simon Guinota35cb4c2011-11-21 19:25:47 +05301/*
2 * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Simon Guinota35cb4c2011-11-21 19:25:47 +05305 */
6
7#include <common.h>
8#include <i2c.h>
9#include <miiphy.h>
10
11#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
12
Simon Guinot13c5ae62012-09-06 10:51:42 +000013#define MII_MARVELL_PHY_PAGE 22
14
Simon Guinota35cb4c2011-11-21 19:25:47 +053015#define MV88E1116_LED_FCTRL_REG 10
16#define MV88E1116_CPRSP_CR3_REG 21
17#define MV88E1116_MAC_CTRL_REG 21
Simon Guinota35cb4c2011-11-21 19:25:47 +053018#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
19#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
20
Simon Guinot0473b682012-06-05 13:16:00 +000021void mv_phy_88e1116_init(const char *name, u16 phyaddr)
Simon Guinota35cb4c2011-11-21 19:25:47 +053022{
23 u16 reg;
Simon Guinota35cb4c2011-11-21 19:25:47 +053024
25 if (miiphy_set_current_dev(name))
26 return;
27
Simon Guinota35cb4c2011-11-21 19:25:47 +053028 /*
29 * Enable RGMII delay on Tx and Rx for CPU port
30 * Ref: sec 4.7.2 of chip datasheet
31 */
Simon Guinot13c5ae62012-09-06 10:51:42 +000032 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
Simon Guinot0473b682012-06-05 13:16:00 +000033 miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
Simon Guinota35cb4c2011-11-21 19:25:47 +053034 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
Simon Guinot0473b682012-06-05 13:16:00 +000035 miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
Simon Guinot13c5ae62012-09-06 10:51:42 +000036 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
Simon Guinota35cb4c2011-11-21 19:25:47 +053037
Simon Guinot0473b682012-06-05 13:16:00 +000038 if (miiphy_reset(name, phyaddr) == 0)
39 printf("88E1116 Initialized on %s\n", name);
Simon Guinota35cb4c2011-11-21 19:25:47 +053040}
Simon Guinot13c5ae62012-09-06 10:51:42 +000041
42void mv_phy_88e1318_init(const char *name, u16 phyaddr)
43{
44 u16 reg;
45
46 if (miiphy_set_current_dev(name))
47 return;
48
49 /*
50 * Set control mode 4 for LED[0].
51 */
52 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
53 miiphy_read(name, phyaddr, 16, &reg);
54 reg |= 0xf;
55 miiphy_write(name, phyaddr, 16, reg);
56
57 /*
58 * Enable RGMII delay on Tx and Rx for CPU port
59 * Ref: sec 4.7.2 of chip datasheet
60 */
61 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
62 miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
63 reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
64 miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
65 miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
66
67 if (miiphy_reset(name, phyaddr) == 0)
68 printf("88E1318 Initialized on %s\n", name);
69}
Simon Guinota35cb4c2011-11-21 19:25:47 +053070#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
71
72#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
73int lacie_read_mac_address(uchar *mac_addr)
74{
75 int ret;
76 ushort version;
77
78 /* I2C-0 for on-board EEPROM */
79 i2c_set_bus_num(0);
80
81 /* Check layout version for EEPROM data */
82 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
83 CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
84 (uchar *) &version, 2);
85 if (ret != 0) {
86 printf("Error: failed to read I2C EEPROM @%02x\n",
87 CONFIG_SYS_I2C_EEPROM_ADDR);
88 return ret;
89 }
90 version = be16_to_cpu(version);
91 if (version < 1 || version > 3) {
92 printf("Error: unknown version %d for EEPROM data\n",
93 version);
94 return -1;
95 }
96
97 /* Read Ethernet MAC address from EEPROM */
98 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2,
99 CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6);
100 if (ret != 0)
101 printf("Error: failed to read I2C EEPROM @%02x\n",
102 CONFIG_SYS_I2C_EEPROM_ADDR);
103 return ret;
104}
105#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */