| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Ludovic Desroches | 9334e99 | 2017-11-17 14:57:11 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017 Microchip Corporation. |
| 4 | * |
| 5 | * Static Memory Controllers (SMC) - System peripherals registers. |
| 6 | * Based on SAMA5D2 datasheet. |
| Ludovic Desroches | 9334e99 | 2017-11-17 14:57:11 +0800 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef SAMA5D2_SMC_H |
| 10 | #define SAMA5D2_SMC_H |
| 11 | |
| 12 | #ifdef __ASSEMBLY__ |
| 13 | #define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x700) |
| 14 | #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x704) |
| 15 | #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x708) |
| 16 | #define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x70c) |
| 17 | #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x710) |
| 18 | #else |
| 19 | struct at91_cs { |
| 20 | u32 setup; /* 0x600 SMC Setup Register */ |
| 21 | u32 pulse; /* 0x604 SMC Pulse Register */ |
| 22 | u32 cycle; /* 0x608 SMC Cycle Register */ |
| 23 | u32 timings; /* 0x60C SMC Cycle Register */ |
| 24 | u32 mode; /* 0x610 SMC Mode Register */ |
| 25 | }; |
| 26 | |
| 27 | struct at91_smc { |
| 28 | struct at91_cs cs[4]; |
| 29 | }; |
| 30 | #endif /* __ASSEMBLY__ */ |
| 31 | |
| 32 | #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) |
| 33 | #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) |
| 34 | #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) |
| 35 | #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) |
| 36 | |
| 37 | #define AT91_SMC_PULSE_NWE(x) (x & 0x7f) |
| 38 | #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) |
| 39 | #define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) |
| 40 | #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) |
| 41 | |
| 42 | #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) |
| 43 | #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) |
| 44 | |
| 45 | #define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf) |
| 46 | #define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4) |
| 47 | #define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8) |
| 48 | #define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12) |
| 49 | #define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16) |
| 50 | #define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24) |
| 51 | #define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28) |
| 52 | #define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31) |
| 53 | |
| 54 | #define AT91_SMC_MODE_RM_NCS 0x00000000 |
| 55 | #define AT91_SMC_MODE_RM_NRD 0x00000001 |
| 56 | #define AT91_SMC_MODE_WM_NCS 0x00000000 |
| 57 | #define AT91_SMC_MODE_WM_NWE 0x00000002 |
| 58 | |
| 59 | #define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 |
| 60 | #define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 |
| 61 | #define AT91_SMC_MODE_EXNW_READY 0x00000030 |
| 62 | |
| 63 | #define AT91_SMC_MODE_BAT 0x00000100 |
| 64 | #define AT91_SMC_MODE_DBW_8 0x00000000 |
| 65 | #define AT91_SMC_MODE_DBW_16 0x00001000 |
| 66 | #define AT91_SMC_MODE_DBW_32 0x00002000 |
| 67 | #define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) |
| 68 | #define AT91_SMC_MODE_TDF 0x00100000 |
| 69 | #define AT91_SMC_MODE_PMEN 0x01000000 |
| 70 | #define AT91_SMC_MODE_PS_4 0x00000000 |
| 71 | #define AT91_SMC_MODE_PS_8 0x10000000 |
| 72 | #define AT91_SMC_MODE_PS_16 0x20000000 |
| 73 | #define AT91_SMC_MODE_PS_32 0x30000000 |
| 74 | |
| 75 | #endif |