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git01.mediatek.com / filogic / uboot / a611ffc8cc87834ab6e52e2f8c82df85140c9905 / . / arch / arm / dts / imx53.dtsi
blob: f68e88585e42d84fa7c40eb2fa213a3c8c89bf4e [file] [log] [blame]
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]1/*
2 * Copyright 2016 Beckhoff Automation
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include "skeleton.dtsi"
15#include "imx53-pinfunc.h"
16#include <dt-bindings/clock/imx5-clock.h>
17#include <dt-bindings/gpio/gpio.h>
18#include <dt-bindings/input/input.h>
19#include <dt-bindings/interrupt-controller/irq.h>
20
21/ {
22 aliases {
23 serial1 = &uart2;
24 };
25
Patrick Bruenn44b21332017-12-11 13:09:14 +0100[diff] [blame]26 tzic: tz-interrupt-controller@fffc000 {
27 compatible = "fsl,imx53-tzic", "fsl,tzic";
28 interrupt-controller;
29 #interrupt-cells = <1>;
30 reg = <0x0fffc000 0x4000>;
31 };
32
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]33 soc {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "simple-bus";
Patrick Bruenn44b21332017-12-11 13:09:14 +0100[diff] [blame]37 interrupt-parent = <&tzic>;
Patrick Bruennba81b042016-11-04 11:57:02 +0100[diff] [blame]38 ranges;
39
40 aips@50000000 { /* AIPS1 */
41 compatible = "fsl,aips-bus", "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 reg = <0x50000000 0x10000000>;
45 ranges;
46
47 iomuxc: iomuxc@53fa8000 {
48 compatible = "fsl,imx53-iomuxc";
49 reg = <0x53fa8000 0x4000>;
50 };
51
52 gpr: iomuxc-gpr@53fa8000 {
53 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
54 reg = <0x53fa8000 0xc>;
55 };
56
57 uart2: serial@53fc0000 {
58 compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
59 reg = <0x53fc0000 0x4000>;
60 interrupts = <32>;
61 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
62 <&clks IMX5_CLK_UART2_PER_GATE>;
63 clock-names = "ipg", "per";
64 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
65 dma-names = "rx", "tx";
66 status = "disabled";
67 };
68
69 clks: ccm@53fd4000{
70 compatible = "fsl,imx53-ccm";
71 reg = <0x53fd4000 0x4000>;
72 interrupts = <0 71 0x04 0 72 0x04>;
73 #clock-cells = <1>;
74 };
75
76 gpio7: gpio@53fe4000 {
77 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
78 reg = <0x53fe4000 0x4000>;
79 interrupts = <107 108>;
80 gpio-controller;
81 #gpio-cells = <2>;
82 interrupt-controller;
83 #interrupt-cells = <2>;
84 };
85 };
86
87 aips@60000000 { /* AIPS2 */
88 compatible = "fsl,aips-bus", "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 reg = <0x60000000 0x10000000>;
92 ranges;
93
94 sdma: sdma@63fb0000 {
95 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
96 reg = <0x63fb0000 0x4000>;
97 interrupts = <6>;
98 clocks = <&clks IMX5_CLK_SDMA_GATE>,
99 <&clks IMX5_CLK_SDMA_GATE>;
100 clock-names = "ipg", "ahb";
101 #dma-cells = <3>;
102 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
103 };
104
105
106 fec: ethernet@63fec000 {
107 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
108 reg = <0x63fec000 0x4000>;
109 interrupts = <87>;
110 clocks = <&clks IMX5_CLK_FEC_GATE>,
111 <&clks IMX5_CLK_FEC_GATE>,
112 <&clks IMX5_CLK_FEC_GATE>;
113 clock-names = "ipg", "ahb", "ptp";
114 status = "disabled";
115 };
116 };
117 };
118};