| Simon Glass | b3f0756 | 2016-01-21 19:44:54 -0700 | [diff] [blame] | 1 | config DM_PWM |
| 2 | bool "Enable support for pulse-width modulation devices (PWM)" |
| 3 | depends on DM |
| 4 | help |
| 5 | A pulse-width modulator emits a pulse of varying width and provides |
| 6 | control over the duty cycle (high and low time) of the signal. This |
| 7 | is often used to control a voltage level. The more time the PWM |
| 8 | spends in the 'high' state, the higher the voltage. The PWM's |
| 9 | frequency/period can be controlled along with the proportion of that |
| 10 | time that the signal is high. |
| Simon Glass | c5915f7 | 2016-01-21 19:44:55 -0700 | [diff] [blame] | 11 | |
| Simon Glass | 636bf17 | 2016-02-21 21:08:49 -0700 | [diff] [blame] | 12 | config PWM_EXYNOS |
| 13 | bool "Enable support for the Exynos PWM" |
| 14 | depends on DM_PWM |
| 15 | help |
| 16 | This PWM is found on Samsung Exynos 5250 and other Samsung SoCs. It |
| 17 | supports a programmable period and duty cycle. A 32-bit counter is |
| 18 | used. It provides 5 channels which can be independently |
| 19 | programmed. Channel 4 (the last) is normally used as a timer. |
| 20 | |
| Simon Glass | c5915f7 | 2016-01-21 19:44:55 -0700 | [diff] [blame] | 21 | config PWM_ROCKCHIP |
| 22 | bool "Enable support for the Rockchip PWM" |
| 23 | depends on DM_PWM |
| 24 | help |
| 25 | This PWM is found on RK3288 and other Rockchip SoCs. It supports a |
| 26 | programmable period and duty cycle. A 32-bit counter is used. |
| 27 | Various options provided in the hardware (such as capture mode and |
| 28 | continuous/single-shot) are not supported by the driver. |
| Simon Glass | 90836ff | 2016-01-30 16:38:00 -0700 | [diff] [blame] | 29 | |
| Simon Glass | e62f4be | 2017-04-16 21:01:11 -0600 | [diff] [blame] | 30 | config PWM_SANDBOX |
| 31 | bool "Enable support for the sandbox PWM" |
| 32 | help |
| 33 | This is a sandbox PWM used for testing. It provides 3 channels and |
| 34 | records the settings passed into it, but otherwise does nothing |
| 35 | useful. The PWM can be enabled but is not connected to any outputs |
| 36 | so this is not very useful. |
| 37 | |
| Simon Glass | 90836ff | 2016-01-30 16:38:00 -0700 | [diff] [blame] | 38 | config PWM_TEGRA |
| 39 | bool "Enable support for the Tegra PWM" |
| Simon Glass | d8af3c9 | 2016-01-30 16:38:01 -0700 | [diff] [blame] | 40 | depends on DM_PWM |
| Simon Glass | 90836ff | 2016-01-30 16:38:00 -0700 | [diff] [blame] | 41 | help |
| 42 | This PWM is found on Tegra 20 and other Nvidia SoCs. It supports |
| 43 | four channels with a programmable period and duty cycle. Only a |
| 44 | 32KHz clock is supported by the driver but the duty cycle is |
| 45 | configurable. |
| Vasily Khoruzhick | 86a38e5 | 2018-05-14 08:16:20 -0700 | [diff] [blame] | 46 | |
| 47 | config PWM_SUNXI |
| 48 | bool "Enable support for the Allwinner Sunxi PWM" |
| 49 | depends on DM_PWM |
| 50 | help |
| 51 | This PWM is found on H3, A64 and other Allwinner SoCs. It supports a |
| 52 | programmable period and duty cycle. A 16-bit counter is used. |