Etienne Carriere | 02fd126 | 2020-09-09 18:44:00 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
| 2 | /* |
| 3 | * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. |
| 4 | * Copyright (C) 2019-2020, Linaro Limited |
| 5 | */ |
| 6 | #ifndef _SCMI_PROTOCOLS_H |
| 7 | #define _SCMI_PROTOCOLS_H |
| 8 | |
| 9 | #include <linux/bitops.h> |
Etienne Carriere | 78928e1 | 2020-09-09 18:44:04 +0200 | [diff] [blame] | 10 | #include <asm/types.h> |
Etienne Carriere | 02fd126 | 2020-09-09 18:44:00 +0200 | [diff] [blame] | 11 | |
| 12 | /* |
| 13 | * Subset the SCMI protocols definition |
| 14 | * based on SCMI specification v2.0 (DEN0056B) |
| 15 | * https://developer.arm.com/docs/den0056/b |
| 16 | */ |
| 17 | |
| 18 | enum scmi_std_protocol { |
| 19 | SCMI_PROTOCOL_ID_BASE = 0x10, |
| 20 | SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11, |
| 21 | SCMI_PROTOCOL_ID_SYSTEM = 0x12, |
| 22 | SCMI_PROTOCOL_ID_PERF = 0x13, |
| 23 | SCMI_PROTOCOL_ID_CLOCK = 0x14, |
| 24 | SCMI_PROTOCOL_ID_SENSOR = 0x15, |
| 25 | SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16, |
Etienne Carriere | d68663a | 2021-03-08 22:38:06 +0100 | [diff] [blame] | 26 | SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN = 0x17, |
Etienne Carriere | 02fd126 | 2020-09-09 18:44:00 +0200 | [diff] [blame] | 27 | }; |
| 28 | |
| 29 | enum scmi_status_code { |
| 30 | SCMI_SUCCESS = 0, |
| 31 | SCMI_NOT_SUPPORTED = -1, |
| 32 | SCMI_INVALID_PARAMETERS = -2, |
| 33 | SCMI_DENIED = -3, |
| 34 | SCMI_NOT_FOUND = -4, |
| 35 | SCMI_OUT_OF_RANGE = -5, |
| 36 | SCMI_BUSY = -6, |
| 37 | SCMI_COMMS_ERROR = -7, |
| 38 | SCMI_GENERIC_ERROR = -8, |
| 39 | SCMI_HARDWARE_ERROR = -9, |
| 40 | SCMI_PROTOCOL_ERROR = -10, |
| 41 | }; |
| 42 | |
Etienne Carriere | 78928e1 | 2020-09-09 18:44:04 +0200 | [diff] [blame] | 43 | /* |
Etienne Carriere | 4c4ec90 | 2022-02-21 09:22:42 +0100 | [diff] [blame] | 44 | * Generic message IDs |
| 45 | */ |
| 46 | enum scmi_discovery_id { |
| 47 | SCMI_PROTOCOL_VERSION = 0x0, |
| 48 | SCMI_PROTOCOL_ATTRIBUTES = 0x1, |
| 49 | SCMI_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2, |
| 50 | }; |
| 51 | |
| 52 | /* |
Etienne Carriere | 78928e1 | 2020-09-09 18:44:04 +0200 | [diff] [blame] | 53 | * SCMI Clock Protocol |
| 54 | */ |
| 55 | |
| 56 | enum scmi_clock_message_id { |
Etienne Carriere | 4c4ec90 | 2022-02-21 09:22:42 +0100 | [diff] [blame] | 57 | SCMI_CLOCK_ATTRIBUTES = 0x3, |
Etienne Carriere | 78928e1 | 2020-09-09 18:44:04 +0200 | [diff] [blame] | 58 | SCMI_CLOCK_RATE_SET = 0x5, |
| 59 | SCMI_CLOCK_RATE_GET = 0x6, |
| 60 | SCMI_CLOCK_CONFIG_SET = 0x7, |
| 61 | }; |
| 62 | |
Etienne Carriere | 4c4ec90 | 2022-02-21 09:22:42 +0100 | [diff] [blame] | 63 | #define SCMI_CLK_PROTO_ATTR_COUNT_MASK GENMASK(15, 0) |
Etienne Carriere | 78928e1 | 2020-09-09 18:44:04 +0200 | [diff] [blame] | 64 | #define SCMI_CLK_RATE_ASYNC_NOTIFY BIT(0) |
| 65 | #define SCMI_CLK_RATE_ASYNC_NORESP (BIT(0) | BIT(1)) |
| 66 | #define SCMI_CLK_RATE_ROUND_DOWN 0 |
| 67 | #define SCMI_CLK_RATE_ROUND_UP BIT(2) |
| 68 | #define SCMI_CLK_RATE_ROUND_CLOSEST BIT(3) |
| 69 | |
Etienne Carriere | 4c4ec90 | 2022-02-21 09:22:42 +0100 | [diff] [blame] | 70 | #define SCMI_CLOCK_NAME_LENGTH_MAX 16 |
| 71 | |
| 72 | /** |
| 73 | * struct scmi_clk_get_nb_out - Response for SCMI_PROTOCOL_ATTRIBUTES command |
| 74 | * @status: SCMI command status |
| 75 | * @attributes: Attributes of the clock protocol, mainly number of clocks exposed |
| 76 | */ |
| 77 | struct scmi_clk_protocol_attr_out { |
| 78 | s32 status; |
| 79 | u32 attributes; |
| 80 | }; |
| 81 | |
| 82 | /** |
| 83 | * struct scmi_clk_attribute_in - Message payload for SCMI_CLOCK_ATTRIBUTES command |
| 84 | * @clock_id: SCMI clock ID |
| 85 | */ |
| 86 | struct scmi_clk_attribute_in { |
| 87 | u32 clock_id; |
| 88 | }; |
| 89 | |
| 90 | /** |
| 91 | * struct scmi_clk_get_nb_out - Response payload for SCMI_CLOCK_ATTRIBUTES command |
| 92 | * @status: SCMI command status |
| 93 | * @attributes: clock attributes |
| 94 | * @clock_name: name of the clock |
| 95 | */ |
| 96 | struct scmi_clk_attribute_out { |
| 97 | s32 status; |
| 98 | u32 attributes; |
| 99 | char clock_name[SCMI_CLOCK_NAME_LENGTH_MAX]; |
| 100 | }; |
| 101 | |
Etienne Carriere | 78928e1 | 2020-09-09 18:44:04 +0200 | [diff] [blame] | 102 | /** |
| 103 | * struct scmi_clk_state_in - Message payload for CLOCK_CONFIG_SET command |
| 104 | * @clock_id: SCMI clock ID |
| 105 | * @attributes: Attributes of the targets clock state |
| 106 | */ |
| 107 | struct scmi_clk_state_in { |
| 108 | u32 clock_id; |
| 109 | u32 attributes; |
| 110 | }; |
| 111 | |
| 112 | /** |
| 113 | * struct scmi_clk_state_out - Response payload for CLOCK_CONFIG_SET command |
| 114 | * @status: SCMI command status |
| 115 | */ |
| 116 | struct scmi_clk_state_out { |
| 117 | s32 status; |
| 118 | }; |
| 119 | |
| 120 | /** |
| 121 | * struct scmi_clk_state_in - Message payload for CLOCK_RATE_GET command |
| 122 | * @clock_id: SCMI clock ID |
| 123 | * @attributes: Attributes of the targets clock state |
| 124 | */ |
| 125 | struct scmi_clk_rate_get_in { |
| 126 | u32 clock_id; |
| 127 | }; |
| 128 | |
| 129 | /** |
| 130 | * struct scmi_clk_rate_get_out - Response payload for CLOCK_RATE_GET command |
| 131 | * @status: SCMI command status |
| 132 | * @rate_lsb: 32bit LSB of the clock rate in Hertz |
| 133 | * @rate_msb: 32bit MSB of the clock rate in Hertz |
| 134 | */ |
| 135 | struct scmi_clk_rate_get_out { |
| 136 | s32 status; |
| 137 | u32 rate_lsb; |
| 138 | u32 rate_msb; |
| 139 | }; |
| 140 | |
| 141 | /** |
| 142 | * struct scmi_clk_state_in - Message payload for CLOCK_RATE_SET command |
Etienne Carriere | 78928e1 | 2020-09-09 18:44:04 +0200 | [diff] [blame] | 143 | * @flags: Flags for the clock rate set request |
Clément Léger | d5e3abb | 2021-10-13 16:00:04 +0200 | [diff] [blame] | 144 | * @clock_id: SCMI clock ID |
Etienne Carriere | 78928e1 | 2020-09-09 18:44:04 +0200 | [diff] [blame] | 145 | * @rate_lsb: 32bit LSB of the clock rate in Hertz |
| 146 | * @rate_msb: 32bit MSB of the clock rate in Hertz |
| 147 | */ |
| 148 | struct scmi_clk_rate_set_in { |
Etienne Carriere | 78928e1 | 2020-09-09 18:44:04 +0200 | [diff] [blame] | 149 | u32 flags; |
Clément Léger | d5e3abb | 2021-10-13 16:00:04 +0200 | [diff] [blame] | 150 | u32 clock_id; |
Etienne Carriere | 78928e1 | 2020-09-09 18:44:04 +0200 | [diff] [blame] | 151 | u32 rate_lsb; |
| 152 | u32 rate_msb; |
| 153 | }; |
| 154 | |
| 155 | /** |
| 156 | * struct scmi_clk_rate_set_out - Response payload for CLOCK_RATE_SET command |
| 157 | * @status: SCMI command status |
| 158 | */ |
| 159 | struct scmi_clk_rate_set_out { |
| 160 | s32 status; |
| 161 | }; |
| 162 | |
Etienne Carriere | c6e9af3 | 2020-09-09 18:44:06 +0200 | [diff] [blame] | 163 | /* |
| 164 | * SCMI Reset Domain Protocol |
| 165 | */ |
| 166 | |
| 167 | enum scmi_reset_domain_message_id { |
| 168 | SCMI_RESET_DOMAIN_ATTRIBUTES = 0x3, |
| 169 | SCMI_RESET_DOMAIN_RESET = 0x4, |
| 170 | }; |
| 171 | |
| 172 | #define SCMI_RD_NAME_LEN 16 |
| 173 | |
| 174 | #define SCMI_RD_ATTRIBUTES_FLAG_ASYNC BIT(31) |
| 175 | #define SCMI_RD_ATTRIBUTES_FLAG_NOTIF BIT(30) |
| 176 | |
| 177 | #define SCMI_RD_RESET_FLAG_ASYNC BIT(2) |
| 178 | #define SCMI_RD_RESET_FLAG_ASSERT BIT(1) |
| 179 | #define SCMI_RD_RESET_FLAG_CYCLE BIT(0) |
| 180 | |
| 181 | /** |
| 182 | * struct scmi_rd_attr_in - Payload for RESET_DOMAIN_ATTRIBUTES message |
| 183 | * @domain_id: SCMI reset domain ID |
| 184 | */ |
| 185 | struct scmi_rd_attr_in { |
| 186 | u32 domain_id; |
| 187 | }; |
| 188 | |
| 189 | /** |
| 190 | * struct scmi_rd_attr_out - Payload for RESET_DOMAIN_ATTRIBUTES response |
| 191 | * @status: SCMI command status |
| 192 | * @attributes: Retrieved attributes of the reset domain |
| 193 | * @latency: Reset cycle max lantency |
| 194 | * @name: Reset domain name |
| 195 | */ |
| 196 | struct scmi_rd_attr_out { |
| 197 | s32 status; |
| 198 | u32 attributes; |
| 199 | u32 latency; |
| 200 | char name[SCMI_RD_NAME_LEN]; |
| 201 | }; |
| 202 | |
| 203 | /** |
| 204 | * struct scmi_rd_reset_in - Message payload for RESET command |
| 205 | * @domain_id: SCMI reset domain ID |
| 206 | * @flags: Flags for the reset request |
| 207 | * @reset_state: Reset target state |
| 208 | */ |
| 209 | struct scmi_rd_reset_in { |
| 210 | u32 domain_id; |
| 211 | u32 flags; |
| 212 | u32 reset_state; |
| 213 | }; |
| 214 | |
| 215 | /** |
| 216 | * struct scmi_rd_reset_out - Response payload for RESET command |
| 217 | * @status: SCMI command status |
| 218 | */ |
| 219 | struct scmi_rd_reset_out { |
| 220 | s32 status; |
| 221 | }; |
| 222 | |
Etienne Carriere | d68663a | 2021-03-08 22:38:06 +0100 | [diff] [blame] | 223 | /* |
| 224 | * SCMI Voltage Domain Protocol |
| 225 | */ |
| 226 | |
| 227 | enum scmi_voltage_domain_message_id { |
| 228 | SCMI_VOLTAGE_DOMAIN_ATTRIBUTES = 0x3, |
| 229 | SCMI_VOLTAGE_DOMAIN_CONFIG_SET = 0x5, |
| 230 | SCMI_VOLTAGE_DOMAIN_CONFIG_GET = 0x6, |
| 231 | SCMI_VOLTAGE_DOMAIN_LEVEL_SET = 0x7, |
| 232 | SCMI_VOLTAGE_DOMAIN_LEVEL_GET = 0x8, |
| 233 | }; |
| 234 | |
| 235 | #define SCMI_VOLTD_NAME_LEN 16 |
| 236 | |
| 237 | #define SCMI_VOLTD_CONFIG_MASK GENMASK(3, 0) |
| 238 | #define SCMI_VOLTD_CONFIG_OFF 0 |
| 239 | #define SCMI_VOLTD_CONFIG_ON 0x7 |
| 240 | |
| 241 | /** |
| 242 | * struct scmi_voltd_attr_in - Payload for VOLTAGE_DOMAIN_ATTRIBUTES message |
| 243 | * @domain_id: SCMI voltage domain ID |
| 244 | */ |
| 245 | struct scmi_voltd_attr_in { |
| 246 | u32 domain_id; |
| 247 | }; |
| 248 | |
| 249 | /** |
| 250 | * struct scmi_voltd_attr_out - Payload for VOLTAGE_DOMAIN_ATTRIBUTES response |
| 251 | * @status: SCMI command status |
| 252 | * @attributes: Retrieved attributes of the voltage domain |
| 253 | * @name: Voltage domain name |
| 254 | */ |
| 255 | struct scmi_voltd_attr_out { |
| 256 | s32 status; |
| 257 | u32 attributes; |
| 258 | char name[SCMI_VOLTD_NAME_LEN]; |
| 259 | }; |
| 260 | |
| 261 | /** |
| 262 | * struct scmi_voltd_config_set_in - Message payload for VOLTAGE_CONFIG_SET cmd |
| 263 | * @domain_id: SCMI voltage domain ID |
| 264 | * @config: Configuration data of the voltage domain |
| 265 | */ |
| 266 | struct scmi_voltd_config_set_in { |
| 267 | u32 domain_id; |
| 268 | u32 config; |
| 269 | }; |
| 270 | |
| 271 | /** |
| 272 | * struct scmi_voltd_config_set_out - Response for VOLTAGE_CONFIG_SET command |
| 273 | * @status: SCMI command status |
| 274 | */ |
| 275 | struct scmi_voltd_config_set_out { |
| 276 | s32 status; |
| 277 | }; |
| 278 | |
| 279 | /** |
| 280 | * struct scmi_voltd_config_get_in - Message payload for VOLTAGE_CONFIG_GET cmd |
| 281 | * @domain_id: SCMI voltage domain ID |
| 282 | */ |
| 283 | struct scmi_voltd_config_get_in { |
| 284 | u32 domain_id; |
| 285 | }; |
| 286 | |
| 287 | /** |
| 288 | * struct scmi_voltd_config_get_out - Response for VOLTAGE_CONFIG_GET command |
| 289 | * @status: SCMI command status |
| 290 | * @config: Configuration data of the voltage domain |
| 291 | */ |
| 292 | struct scmi_voltd_config_get_out { |
| 293 | s32 status; |
| 294 | u32 config; |
| 295 | }; |
| 296 | |
| 297 | /** |
| 298 | * struct scmi_voltd_level_set_in - Message payload for VOLTAGE_LEVEL_SET cmd |
| 299 | * @domain_id: SCMI voltage domain ID |
| 300 | * @flags: Parameter flags for configuring target level |
| 301 | * @voltage_level: Target voltage level in microvolts (uV) |
| 302 | */ |
| 303 | struct scmi_voltd_level_set_in { |
| 304 | u32 domain_id; |
| 305 | u32 flags; |
| 306 | s32 voltage_level; |
| 307 | }; |
| 308 | |
| 309 | /** |
| 310 | * struct scmi_voltd_level_set_out - Response for VOLTAGE_LEVEL_SET command |
| 311 | * @status: SCMI command status |
| 312 | */ |
| 313 | struct scmi_voltd_level_set_out { |
| 314 | s32 status; |
| 315 | }; |
| 316 | |
| 317 | /** |
| 318 | * struct scmi_voltd_level_get_in - Message payload for VOLTAGE_LEVEL_GET cmd |
| 319 | * @domain_id: SCMI voltage domain ID |
| 320 | */ |
| 321 | struct scmi_voltd_level_get_in { |
| 322 | u32 domain_id; |
| 323 | }; |
| 324 | |
| 325 | /** |
| 326 | * struct scmi_voltd_level_get_out - Response for VOLTAGE_LEVEL_GET command |
| 327 | * @status: SCMI command status |
| 328 | * @voltage_level: Voltage level in microvolts (uV) |
| 329 | */ |
| 330 | struct scmi_voltd_level_get_out { |
| 331 | s32 status; |
| 332 | s32 voltage_level; |
| 333 | }; |
| 334 | |
Etienne Carriere | 02fd126 | 2020-09-09 18:44:00 +0200 | [diff] [blame] | 335 | #endif /* _SCMI_PROTOCOLS_H */ |