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git01.mediatek.com / filogic / uboot / a5b4bdbda8ccd90e08ff2f5b643b50a27d45178e / . / board / freescale / imx8mq_evk / imx8mq_evk.c
blob: e39480585609de4b0ddc9fa0104665db6e7df1b6 [file] [log] [blame]
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -0600[diff] [blame]7#include <env.h>
Simon Glassa7b51302019-11-14 12:57:46 -0700[diff] [blame]8#include <init.h>
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]9#include <malloc.h>
10#include <errno.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame]11#include <asm/global_data.h>
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]12#include <asm/io.h>
13#include <miiphy.h>
14#include <netdev.h>
15#include <asm/mach-imx/iomux-v3.h>
16#include <asm-generic/gpio.h>
Yangbo Lu73340382019-06-21 11:42:28 +0800[diff] [blame]17#include <fsl_esdhc_imx.h>
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]18#include <mmc.h>
19#include <asm/arch/imx8mq_pins.h>
20#include <asm/arch/sys_proto.h>
21#include <asm/mach-imx/gpio.h>
22#include <asm/mach-imx/mxc_i2c.h>
23#include <asm/arch/clock.h>
24#include <spl.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]25#include <linux/bitops.h>
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]26#include <power/pmic.h>
27#include <power/pfuze100_pmic.h>
28#include "../common/pfuze.h"
29
30DECLARE_GLOBAL_DATA_PTR;
31
32#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
33
34#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
35
36static iomux_v3_cfg_t const wdog_pads[] = {
37 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
38};
39
40static iomux_v3_cfg_t const uart_pads[] = {
41 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
42 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
43};
44
45int board_early_init_f(void)
46{
47 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
48
49 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
50 set_wdog_reset(wdog);
51
52 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
53
54 return 0;
55}
56
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]57#ifdef CONFIG_FEC_MXC
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]58static int setup_fec(void)
59{
60 struct iomuxc_gpr_base_regs *gpr =
61 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
62
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]63 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
64 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
65 return set_clk_enet(ENET_125MHZ);
66}
67
68int board_phy_config(struct phy_device *phydev)
69{
70 /* enable rgmii rxc skew and phy mode select to RGMII copper */
71 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
72 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
73
74 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
75 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
76
77 if (phydev->drv->config)
78 phydev->drv->config(phydev);
79 return 0;
80}
81#endif
82
83int board_init(void)
84{
85#ifdef CONFIG_FEC_MXC
86 setup_fec();
87#endif
88
Ye Li55fc7822021-02-21 08:26:24 -0800[diff] [blame]89#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
90 init_usb_clk();
91#endif
92
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]93 return 0;
94}
95
96int board_mmc_get_env_dev(int devno)
97{
98 return devno;
99}
100
101int board_late_init(void)
102{
103#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
104 env_set("board_name", "EVK");
105 env_set("board_rev", "iMX8MQ");
106#endif
107
108 return 0;
109}