blob: 2d04521dd679d5e95595b85574cfe22ca2686fb1 [file] [log] [blame]
Ashok Reddy Somaf79b2172022-11-16 07:11:55 -07001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal Mini OSPI Configuration
4 *
5 * (C) Copyright 2018-2019, Xilinx, Inc.
6 *
7 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
8 * Michal Simek <michal.simek@xilinx.com>
9 */
10
11/dts-v1/;
12
13/ {
14 compatible = "xlnx,versal";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 model = "Xilinx Versal MINI OSPI";
18
19 clk125: clk125 {
20 compatible = "fixed-clock";
21 #clock-cells = <0x0>;
22 clock-frequency = <125000000>;
23 };
24
25 dcc: dcc {
26 compatible = "arm,dcc";
27 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -070028 bootph-all;
Ashok Reddy Somaf79b2172022-11-16 07:11:55 -070029 };
30
31 amba: amba {
Simon Glassd3a98cb2023-02-13 08:56:33 -070032 bootph-all;
Ashok Reddy Somaf79b2172022-11-16 07:11:55 -070033 compatible = "simple-bus";
34 #address-cells = <0x2>;
35 #size-cells = <0x2>;
36 ranges;
37
38 ospi: spi@f1010000 {
39 compatible = "cadence,qspi", "cdns,qspi-nor";
40 status = "okay";
41 reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
42 clock-names = "ref_clk", "pclk";
43 clocks = <&clk125 &clk125>;
44 bus-num = <2>;
45 num-cs = <1>;
46 cdns,fifo-depth = <256>;
47 cdns,fifo-width = <4>;
48 cdns,is-dma = <1>;
49 cdns,trigger-address = <0xc0000000>;
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 flash0: flash@0 {
54 compatible = "n25q512a", "micron,m25p80",
55 "jedec,spi-nor";
56 reg = <0x0>;
57 spi-tx-bus-width = <8>;
58 spi-rx-bus-width = <8>;
59 spi-max-frequency = <20000000>;
60 };
61 };
62 };
63
64 aliases {
65 serial0 = &dcc;
66 spi0 = &ospi;
67 };
68
69 chosen {
70 stdout-path = "serial0:115200";
71 };
72
73 memory@fffc0000 {
74 device_type = "memory";
75 reg = <0x0 0xfffc0000 0x0 0x40000>;
76 };
77};