Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / a5b4bdbda8ccd90e08ff2f5b643b50a27d45178e / . / arch / arm / dts / socfpga_agilex-u-boot.dtsi
blob: 4d7680455b774ac4480ca7848e1bd08ea8f9c54f [file] [log] [blame]
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * U-Boot additions
4 *
Siew Chin Lim9fe3a012020-12-24 18:21:11 +0800[diff] [blame]5 * Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]6 */
7
Siew Chin Lim9fe3a012020-12-24 18:21:11 +0800[diff] [blame]8#include "socfpga_soc64_fit-u-boot.dtsi"
9
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]10/{
11 memory {
12 #address-cells = <2>;
13 #size-cells = <2>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]14 bootph-all;
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]15 };
16
17 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-all;
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]19
20 ccu: cache-controller@f7000000 {
21 compatible = "arteris,ncore-ccu";
22 reg = <0xf7000000 0x100900>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]23 bootph-all;
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]24 };
25 };
26};
27
28&clkmgr {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-all;
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]30};
31
32&gmac1 {
33 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
34};
35
36&gmac2 {
37 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
38};
39
40&i2c0 {
41 reset-names = "i2c";
42};
43
44&i2c1 {
45 reset-names = "i2c";
46};
47
48&i2c2 {
49 reset-names = "i2c";
50};
51
52&i2c3 {
53 reset-names = "i2c";
54};
55
56&mmc {
57 resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
58};
59
60&porta {
61 bank-name = "porta";
62};
63
64&portb {
65 bank-name = "portb";
66};
67
68&qspi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-all;
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]70};
71
72&rst {
73 compatible = "altr,rst-mgr";
74 altr,modrst-offset = <0x20>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-all;
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]76};
77
78&sdr {
79 compatible = "intel,sdr-ctl-agilex";
80 reg = <0xf8000400 0x80>,
81 <0xf8010000 0x190>,
82 <0xf8011000 0x500>;
83 resets = <&rst DDRSCH_RESET>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-all;
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]85};
86
87&sysmgr {
88 compatible = "altr,sys-mgr", "syscon";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-all;
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]90};
91
92&uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-all;
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]94};
95
96&watchdog0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-all;
Ley Foon Tand89a1192019-11-27 15:55:30 +0800[diff] [blame]98};