| Simon Glass | 3ed3a4d | 2024-10-23 15:20:10 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-2-Clause-Patent */ |
| 2 | /** |
| 3 | * |
| 4 | * Copyright (c) 2019, Jeremy Linton |
| 5 | * Copyright (c) 2019, Pete Batard <pete@akeo.ie>. |
| 6 | * |
| 7 | **/ |
| 8 | |
| 9 | #ifndef BCM2711_H__ |
| 10 | #define BCM2711_H__ |
| 11 | |
| 12 | #define BCM2711_SOC_REGISTERS 0xfc000000 |
| 13 | #define BCM2711_SOC_REGISTER_LENGTH 0x02000000 |
| 14 | |
| 15 | #define BCM2711_ARM_LOCAL_REGISTERS 0xfe000000 |
| 16 | #define BCM2711_ARM_LOCAL_REGISTER_LENGTH 0x02000000 |
| 17 | |
| 18 | /* arm local addresses */ |
| 19 | #define BCM2711_ARMC_OFFSET 0x0000b000 |
| 20 | #define BCM2711_ARMC_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_ARMC_OFFSET) |
| 21 | #define BCM2711_ARMC_LENGTH 0x00000400 |
| 22 | |
| 23 | #define BCM2711_ARM_LOCAL_OFFSET 0x01800000 |
| 24 | #define BCM2711_ARM_LOCAL_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_ARM_LOCAL_OFFSET) |
| 25 | #define BCM2711_ARM_LOCAL_LENGTH 0x00000080 |
| 26 | |
| 27 | #define BCM2711_GIC400_OFFSET 0x01840000 |
| 28 | #define BCM2711_GIC400_BASE_ADDRESS (BCM2711_ARM_LOCAL_REGISTERS + BCM2711_GIC400_OFFSET) |
| 29 | #define BCM2711_GIC400_LENGTH 0x00008000 |
| 30 | |
| 31 | /* Generic PCI addresses */ |
| 32 | #define PCIE_TOP_OF_MEM_WIN 0xf8000000 |
| 33 | #define PCIE_CPU_MMIO_WINDOW 0x600000000 |
| 34 | #define PCIE_BRIDGE_MMIO_LEN 0x3ffffff |
| 35 | |
| 36 | /* PCI root bridge control registers location */ |
| 37 | #define PCIE_REG_BASE 0xfd500000 |
| 38 | #define PCIE_REG_LIMIT 0x9310 |
| 39 | |
| 40 | /* PCI root bridge control registers */ |
| 41 | #define BRCM_PCIE_CAP_REGS 0x00ac |
| 42 | #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188 |
| 43 | #define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0 |
| 44 | #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c |
| 45 | #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc |
| 46 | #define LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00 |
| 47 | |
| 48 | #define PCIE_RC_DL_MDIO_ADDR 0x1100 |
| 49 | #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 |
| 50 | #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 |
| 51 | |
| 52 | #define PCIE_MISC_MISC_CTRL 0x4008 |
| 53 | #define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 |
| 54 | #define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 |
| 55 | #define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 |
| 56 | #define MISC_CTRL_MAX_BURST_SIZE_128 0x0 |
| 57 | #define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 |
| 58 | |
| 59 | #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c |
| 60 | #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010 |
| 61 | #define PCIE_MEM_WIN0_LO(win) \ |
| 62 | PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4) |
| 63 | |
| 64 | #define PCIE_MEM_WIN0_HI(win) \ |
| 65 | PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4) |
| 66 | #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c |
| 67 | #define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f |
| 68 | #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034 |
| 69 | #define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f |
| 70 | #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 |
| 71 | #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c |
| 72 | #define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f |
| 73 | #define PCIE_MISC_PCIE_STATUS 0x4068 |
| 74 | #define STATUS_PCIE_PORT_MASK 0x80 |
| 75 | #define STATUS_PCIE_PORT_SHIFT 7 |
| 76 | #define STATUS_PCIE_DL_ACTIVE_MASK 0x20 |
| 77 | #define STATUS_PCIE_DL_ACTIVE_SHIFT 5 |
| 78 | #define STATUS_PCIE_PHYLINKUP_MASK 0x10 |
| 79 | #define STATUS_PCIE_PHYLINKUP_SHIFT 4 |
| 80 | #define PCIE_MISC_REVISION 0x406c |
| 81 | #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070 |
| 82 | #define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 |
| 83 | #define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 |
| 84 | #define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12 |
| 85 | #define PCIE_MEM_WIN0_BASE_LIMIT(win) \ |
| 86 | PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4) |
| 87 | #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080 |
| 88 | #define MEM_WIN0_BASE_HI_BASE_MASK 0xff |
| 89 | #define PCIE_MEM_WIN0_BASE_HI(win) \ |
| 90 | PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8) |
| 91 | #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084 |
| 92 | #define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff |
| 93 | #define PCIE_MEM_WIN0_LIMIT_HI(win) \ |
| 94 | PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8) |
| 95 | |
| 96 | #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 |
| 97 | #define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 |
| 98 | |
| 99 | #define PCIE_INTR2_CPU_STATUS 0x4300 |
| 100 | #define PCIE_INTR2_CPU_SET 0x4304 |
| 101 | #define PCIE_INTR2_CPU_CLR 0x4308 |
| 102 | #define PCIE_INTR2_CPU_MASK_STATUS 0x430c |
| 103 | #define PCIE_INTR2_CPU_MASK_SET 0x4310 |
| 104 | #define PCIE_INTR2_CPU_MASK_CLR 0x4314 |
| 105 | |
| 106 | #define PCIE_MSI_INTR2_CLR 0x4508 |
| 107 | #define PCIE_MSI_INTR2_MASK_SET 0x4510 |
| 108 | |
| 109 | #define PCIE_RGR1_SW_INIT_1 0x9210 |
| 110 | #define PCIE_EXT_CFG_INDEX 0x9000 |
| 111 | /* A small window pointing at the ECAM of the device selected by CFG_INDEX */ |
| 112 | #define PCIE_EXT_CFG_DATA 0x8000 |
| 113 | |
| 114 | #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc |
| 115 | #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff |
| 116 | |
| 117 | #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 |
| 118 | #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 |
| 119 | #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 |
| 120 | #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 |
| 121 | #define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000 |
| 122 | #define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f |
| 123 | #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f |
| 124 | |
| 125 | #define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2 |
| 126 | #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1 |
| 127 | |
| 128 | #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 |
| 129 | |
| 130 | #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 |
| 131 | |
| 132 | #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000 |
| 133 | #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0 |
| 134 | #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff |
| 135 | #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff |
| 136 | #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_MASK_BITS 0xc |
| 137 | |
| 138 | #define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff |
| 139 | |
| 140 | #define BURST_SIZE_128 0 |
| 141 | #define BURST_SIZE_256 1 |
| 142 | #define BURST_SIZE_512 2 |
| 143 | |
| 144 | #define BCM2711_THERM_SENSOR_OFFSET 0x015d2200 |
| 145 | #define BCM2711_THERM_SENSOR_BASE_ADDRESS (BCM2711_SOC_REGISTERS + BCM2711_THERM_SENSOR_OFFSET) |
| 146 | #define BCM2711_THERM_SENSOR_LENGTH 0x00000008 |
| 147 | |
| 148 | #define BCM2711_GENET_BASE_OFFSET 0x01580000 |
| 149 | #define BCM2711_GENET_BASE_ADDRESS (BCM2711_SOC_REGISTERS + BCM2711_GENET_BASE_OFFSET) |
| 150 | #define BCM2711_GENET_LENGTH 0x10000 |
| 151 | |
| 152 | #endif /* BCM2711_H__ */ |