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git01.mediatek.com / filogic / uboot / a55e4d42aec0bbc2a129716aebf0bce5bccb1bfa / . / arch / arm / mach-k3 / arm64-mmu.c
blob: 5c858ae0f84e7ca5881e6e6d95bb0c9f8d124f66 [file] [log] [blame]
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * K3: ARM64 MMU setup
4 *
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]5 * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]6 * Lokesh Vutla <lokeshvutla@ti.com>
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]7 * Suman Anna <s-anna@ti.com>
Michal Simek7f60b232019-01-17 08:22:43 +0100[diff] [blame]8 * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]9 *
10 */
11
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]12#include <asm/system.h>
13#include <asm/armv8/mmu.h>
14
Andrew Davis1be5e972022-07-15 10:25:27 -0500[diff] [blame]15#ifdef CONFIG_SOC_K3_AM654
Andrew Davis829b04a2023-11-28 11:05:25 -0600[diff] [blame]16struct mm_region am654_mem_map[] = {
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]17 {
18 .virt = 0x0UL,
19 .phys = 0x0UL,
20 .size = 0x80000000UL,
21 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
22 PTE_BLOCK_NON_SHARE |
23 PTE_BLOCK_PXN | PTE_BLOCK_UXN
24 }, {
25 .virt = 0x80000000UL,
26 .phys = 0x80000000UL,
Andrew Davisa55e4d42023-11-28 11:05:26 -0600[diff] [blame^]27 .size = 0x1e780000UL,
Suman Annaf359afb2019-09-04 16:01:49 +0530[diff] [blame]28 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
29 PTE_BLOCK_INNER_SHARE
30 }, {
31 .virt = 0xa0000000UL,
32 .phys = 0xa0000000UL,
33 .size = 0x02100000UL,
34 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
35 PTE_BLOCK_INNER_SHARE
36 }, {
37 .virt = 0xa2100000UL,
38 .phys = 0xa2100000UL,
39 .size = 0x5df00000UL,
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]40 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
41 PTE_BLOCK_INNER_SHARE
42 }, {
43 .virt = 0x880000000UL,
44 .phys = 0x880000000UL,
45 .size = 0x80000000UL,
46 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
47 PTE_BLOCK_INNER_SHARE
48 }, {
Vignesh Raghavendraf2716382020-02-04 11:09:49 +0530[diff] [blame]49 .virt = 0x500000000UL,
50 .phys = 0x500000000UL,
51 .size = 0x400000000UL,
52 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
53 PTE_BLOCK_NON_SHARE |
54 PTE_BLOCK_PXN | PTE_BLOCK_UXN
55 }, {
Lokesh Vutla49297cf2018-08-27 15:57:13 +0530[diff] [blame]56 /* List terminator */
57 0,
58 }
59};
60
61struct mm_region *mem_map = am654_mem_map;
Andrew Davis1be5e972022-07-15 10:25:27 -0500[diff] [blame]62#endif /* CONFIG_SOC_K3_AM654 */
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]63
64#ifdef CONFIG_SOC_K3_J721E
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]65
Nishanth Menon7fb31d32023-11-04 02:21:46 -0500[diff] [blame]66#ifdef CONFIG_SOC_K3_J721E_J7200
Andrew Davis829b04a2023-11-28 11:05:25 -0600[diff] [blame]67struct mm_region j7200_mem_map[] = {
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]68 {
69 .virt = 0x0UL,
70 .phys = 0x0UL,
71 .size = 0x80000000UL,
72 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
73 PTE_BLOCK_NON_SHARE |
74 PTE_BLOCK_PXN | PTE_BLOCK_UXN
75 }, {
76 .virt = 0x80000000UL,
77 .phys = 0x80000000UL,
Andrew Davisa55e4d42023-11-28 11:05:26 -0600[diff] [blame^]78 .size = 0x1e780000UL,
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]79 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
80 PTE_BLOCK_INNER_SHARE
81 }, {
82 .virt = 0xa0000000UL,
83 .phys = 0xa0000000UL,
Nishanth Menon7fb31d32023-11-04 02:21:46 -0500[diff] [blame]84 .size = 0x04800000UL,
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]85 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
86 PTE_BLOCK_NON_SHARE
87 }, {
Nishanth Menon7fb31d32023-11-04 02:21:46 -0500[diff] [blame]88 .virt = 0xa4800000UL,
89 .phys = 0xa4800000UL,
90 .size = 0x5b800000UL,
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]91 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
92 PTE_BLOCK_INNER_SHARE
93 }, {
94 .virt = 0x880000000UL,
95 .phys = 0x880000000UL,
96 .size = 0x80000000UL,
97 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
98 PTE_BLOCK_INNER_SHARE
99 }, {
100 .virt = 0x500000000UL,
101 .phys = 0x500000000UL,
102 .size = 0x400000000UL,
103 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
104 PTE_BLOCK_NON_SHARE |
105 PTE_BLOCK_PXN | PTE_BLOCK_UXN
106 }, {
107 /* List terminator */
108 0,
109 }
110};
111
Nishanth Menon7fb31d32023-11-04 02:21:46 -0500[diff] [blame]112struct mm_region *mem_map = j7200_mem_map;
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]113
Nishanth Menon7fb31d32023-11-04 02:21:46 -0500[diff] [blame]114#else /* CONFIG_SOC_K3_J721E_J7200 */
Andrew Davis829b04a2023-11-28 11:05:25 -0600[diff] [blame]115struct mm_region j721e_mem_map[] = {
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]116 {
117 .virt = 0x0UL,
118 .phys = 0x0UL,
119 .size = 0x80000000UL,
120 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
121 PTE_BLOCK_NON_SHARE |
122 PTE_BLOCK_PXN | PTE_BLOCK_UXN
123 }, {
124 .virt = 0x80000000UL,
125 .phys = 0x80000000UL,
Andrew Davisa55e4d42023-11-28 11:05:26 -0600[diff] [blame^]126 .size = 0x1e780000UL,
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]127 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
128 PTE_BLOCK_INNER_SHARE
129 }, {
130 .virt = 0xa0000000UL,
131 .phys = 0xa0000000UL,
Nishanth Menon7fb31d32023-11-04 02:21:46 -0500[diff] [blame]132 .size = 0x1bc00000UL,
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]133 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
134 PTE_BLOCK_NON_SHARE
135 }, {
Nishanth Menon7fb31d32023-11-04 02:21:46 -0500[diff] [blame]136 .virt = 0xbbc00000UL,
137 .phys = 0xbbc00000UL,
138 .size = 0x44400000UL,
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]139 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
140 PTE_BLOCK_INNER_SHARE
141 }, {
142 .virt = 0x880000000UL,
143 .phys = 0x880000000UL,
144 .size = 0x80000000UL,
145 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
146 PTE_BLOCK_INNER_SHARE
147 }, {
148 .virt = 0x500000000UL,
149 .phys = 0x500000000UL,
150 .size = 0x400000000UL,
151 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
152 PTE_BLOCK_NON_SHARE |
153 PTE_BLOCK_PXN | PTE_BLOCK_UXN
154 }, {
Nishanth Menon7fb31d32023-11-04 02:21:46 -0500[diff] [blame]155 .virt = 0x4d80000000UL,
156 .phys = 0x4d80000000UL,
157 .size = 0x0002000000UL,
158 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
159 PTE_BLOCK_INNER_SHARE
160 }, {
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]161 /* List terminator */
162 0,
163 }
164};
165
Nishanth Menon7fb31d32023-11-04 02:21:46 -0500[diff] [blame]166struct mm_region *mem_map = j721e_mem_map;
167#endif /* CONFIG_SOC_K3_J721E_J7200 */
Suman Anna0bc221d2020-08-17 18:15:09 -0500[diff] [blame]168
Suman Anna41dfdbf2019-06-13 10:29:48 +0530[diff] [blame]169#endif /* CONFIG_SOC_K3_J721E */
Keerthye07dfe52021-04-23 11:27:39 -0500[diff] [blame]170
David Huang61098202022-01-25 20:56:31 +0530[diff] [blame]171#ifdef CONFIG_SOC_K3_J721S2
Andrew Davis829b04a2023-11-28 11:05:25 -0600[diff] [blame]172struct mm_region j721s2_mem_map[] = {
David Huang61098202022-01-25 20:56:31 +0530[diff] [blame]173 {
174 .virt = 0x0UL,
175 .phys = 0x0UL,
176 .size = 0x80000000UL,
177 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
178 PTE_BLOCK_NON_SHARE |
179 PTE_BLOCK_PXN | PTE_BLOCK_UXN
180 }, {
181 .virt = 0x80000000UL,
182 .phys = 0x80000000UL,
Andrew Davisa55e4d42023-11-28 11:05:26 -0600[diff] [blame^]183 .size = 0x1e780000UL,
184 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
185 PTE_BLOCK_INNER_SHARE
186 }, {
187 .virt = 0xa0000000UL,
188 .phys = 0xa0000000UL,
189 .size = 0x60000000UL,
David Huang61098202022-01-25 20:56:31 +0530[diff] [blame]190 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
191 PTE_BLOCK_INNER_SHARE
192 }, {
193 .virt = 0x880000000UL,
194 .phys = 0x880000000UL,
195 .size = 0x80000000UL,
196 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
197 PTE_BLOCK_INNER_SHARE
198 }, {
199 .virt = 0x500000000UL,
200 .phys = 0x500000000UL,
201 .size = 0x400000000UL,
202 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
203 PTE_BLOCK_NON_SHARE |
204 PTE_BLOCK_PXN | PTE_BLOCK_UXN
205 }, {
206 /* List terminator */
207 0,
208 }
209};
210
211struct mm_region *mem_map = j721s2_mem_map;
212
213#endif /* CONFIG_SOC_K3_J721S2 */
214
Kamlesh Gurudasaniae83fe22023-05-12 17:28:52 +0530[diff] [blame]215#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7)
Bryan Brattlofdaa39a62022-11-03 19:13:55 -0500[diff] [blame]216
Andrew Davis829b04a2023-11-28 11:05:25 -0600[diff] [blame]217struct mm_region am62_mem_map[] = {
Keerthye07dfe52021-04-23 11:27:39 -0500[diff] [blame]218 {
219 .virt = 0x0UL,
220 .phys = 0x0UL,
221 .size = 0x80000000UL,
222 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
223 PTE_BLOCK_NON_SHARE |
224 PTE_BLOCK_PXN | PTE_BLOCK_UXN
225 }, {
226 .virt = 0x80000000UL,
227 .phys = 0x80000000UL,
Kamlesh Gurudasaniae83fe22023-05-12 17:28:52 +0530[diff] [blame]228 .size = 0x1E780000UL,
229 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
230 PTE_BLOCK_INNER_SHARE
231 }, {
232 .virt = 0xA0000000UL,
233 .phys = 0xA0000000UL,
234 .size = 0x60000000UL,
235 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
236 PTE_BLOCK_INNER_SHARE
237
238 }, {
239 .virt = 0x880000000UL,
240 .phys = 0x880000000UL,
241 .size = 0x80000000UL,
242 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
243 PTE_BLOCK_INNER_SHARE
244 }, {
245 .virt = 0x500000000UL,
246 .phys = 0x500000000UL,
247 .size = 0x400000000UL,
248 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
249 PTE_BLOCK_NON_SHARE |
250 PTE_BLOCK_PXN | PTE_BLOCK_UXN
251 }, {
252 /* List terminator */
253 0,
254 }
255};
256
257struct mm_region *mem_map = am62_mem_map;
258#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
259
260#ifdef CONFIG_SOC_K3_AM642
261
Andrew Davis829b04a2023-11-28 11:05:25 -0600[diff] [blame]262struct mm_region am64_mem_map[] = {
Kamlesh Gurudasaniae83fe22023-05-12 17:28:52 +0530[diff] [blame]263 {
264 .virt = 0x0UL,
265 .phys = 0x0UL,
Keerthye07dfe52021-04-23 11:27:39 -0500[diff] [blame]266 .size = 0x80000000UL,
Kamlesh Gurudasaniae83fe22023-05-12 17:28:52 +0530[diff] [blame]267 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
268 PTE_BLOCK_NON_SHARE |
269 PTE_BLOCK_PXN | PTE_BLOCK_UXN
270 }, {
271 .virt = 0x80000000UL,
272 .phys = 0x80000000UL,
273 .size = 0x1E800000UL,
274 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
275 PTE_BLOCK_INNER_SHARE
276 }, {
277 .virt = 0xA0000000UL,
278 .phys = 0xA0000000UL,
279 .size = 0x60000000UL,
Keerthye07dfe52021-04-23 11:27:39 -0500[diff] [blame]280 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
281 PTE_BLOCK_INNER_SHARE
282 }, {
283 .virt = 0x880000000UL,
284 .phys = 0x880000000UL,
285 .size = 0x80000000UL,
286 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
287 PTE_BLOCK_INNER_SHARE
288 }, {
289 .virt = 0x500000000UL,
290 .phys = 0x500000000UL,
291 .size = 0x400000000UL,
292 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
293 PTE_BLOCK_NON_SHARE |
294 PTE_BLOCK_PXN | PTE_BLOCK_UXN
295 }, {
296 /* List terminator */
297 0,
298 }
299};
300
301struct mm_region *mem_map = am64_mem_map;
Kamlesh Gurudasaniae83fe22023-05-12 17:28:52 +0530[diff] [blame]302#endif /* CONFIG_SOC_K3_AM642 */