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Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
5
Simon Glassb2c1cac2014-02-26 15:59:21 -07006/ {
7 model = "sandbox";
8 compatible = "sandbox";
9 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060010 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070011
Simon Glassfef72b72014-07-23 06:55:03 -060012 aliases {
13 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060014 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070015 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060016 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060017 gpio1 = &gpio_a;
18 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010019 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070020 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060021 mmc0 = "/mmc0";
22 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070023 pci0 = &pci0;
24 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070025 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020026 remoteproc0 = &rproc_1;
27 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060028 rtc0 = &rtc_0;
29 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060030 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020031 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070032 testbus3 = "/some-bus";
33 testfdt0 = "/some-bus/c-test@0";
34 testfdt1 = "/some-bus/c-test@1";
35 testfdt3 = "/b-test";
36 testfdt5 = "/some-bus/c-test@5";
37 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020038 fdt-dummy0 = "/translation-test@8000/dev@0,0";
39 fdt-dummy1 = "/translation-test@8000/dev@1,100";
40 fdt-dummy2 = "/translation-test@8000/dev@2,200";
41 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060042 usb0 = &usb_0;
43 usb1 = &usb_1;
44 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020045 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020046 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060047 };
48
Simon Glassed96cde2018-12-10 10:37:33 -070049 audio: audio-codec {
50 compatible = "sandbox,audio-codec";
51 #sound-dai-cells = <1>;
52 };
53
Simon Glassc953aaf2018-12-10 10:37:34 -070054 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060055 reg = <0 0>;
56 compatible = "google,cros-ec-sandbox";
57
58 /*
59 * This describes the flash memory within the EC. Note
60 * that the STM32L flash erases to 0, not 0xff.
61 */
62 flash {
63 image-pos = <0x08000000>;
64 size = <0x20000>;
65 erase-value = <0>;
66
67 /* Information for sandbox */
68 ro {
69 image-pos = <0>;
70 size = <0xf000>;
71 };
72 wp-ro {
73 image-pos = <0xf000>;
74 size = <0x1000>;
75 };
76 rw {
77 image-pos = <0x10000>;
78 size = <0x10000>;
79 };
80 };
81 };
82
Yannick Fertré9712c822019-10-07 15:29:05 +020083 dsi_host: dsi_host {
84 compatible = "sandbox,dsi-host";
85 };
86
Simon Glassb2c1cac2014-02-26 15:59:21 -070087 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -060088 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070089 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -060090 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070091 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -060092 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +010093 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
94 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -070095 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +010096 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
97 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
98 <&gpio_b 7 GPIO_IN 3 2 1>,
99 <&gpio_b 8 GPIO_OUT 3 2 1>,
100 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100101 test3-gpios =
102 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
103 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
104 <&gpio_c 2 GPIO_OUT>,
105 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
106 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200107 <&gpio_c 5 GPIO_IN>,
108 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
109 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Simon Glass6df01f92018-12-10 10:37:37 -0700110 int-value = <1234>;
111 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200112 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200113 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600114 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700115 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600116 acpi,name = "GHIJ";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700117 };
118
119 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600120 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700121 compatible = "not,compatible";
122 };
123
124 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600125 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700126 };
127
Simon Glass5620cf82018-10-01 12:22:40 -0600128 backlight: backlight {
129 compatible = "pwm-backlight";
130 enable-gpios = <&gpio_a 1>;
131 power-supply = <&ldo_1>;
132 pwms = <&pwm 0 1000>;
133 default-brightness-level = <5>;
134 brightness-levels = <0 16 32 64 128 170 202 234 255>;
135 };
136
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200137 bind-test {
138 bind-test-child1 {
139 compatible = "sandbox,phy";
140 #phy-cells = <1>;
141 };
142
143 bind-test-child2 {
144 compatible = "simple-bus";
145 };
146 };
147
Simon Glassb2c1cac2014-02-26 15:59:21 -0700148 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600149 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700150 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600151 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700152 ping-add = <3>;
153 };
154
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200155 phy_provider0: gen_phy@0 {
156 compatible = "sandbox,phy";
157 #phy-cells = <1>;
158 };
159
160 phy_provider1: gen_phy@1 {
161 compatible = "sandbox,phy";
162 #phy-cells = <0>;
163 broken;
164 };
165
developer71092972020-05-02 11:35:12 +0200166 phy_provider2: gen_phy@2 {
167 compatible = "sandbox,phy";
168 #phy-cells = <0>;
169 };
170
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200171 gen_phy_user: gen_phy_user {
172 compatible = "simple-bus";
173 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
174 phy-names = "phy1", "phy2", "phy3";
175 };
176
developer71092972020-05-02 11:35:12 +0200177 gen_phy_user1: gen_phy_user1 {
178 compatible = "simple-bus";
179 phys = <&phy_provider0 0>, <&phy_provider2>;
180 phy-names = "phy1", "phy2";
181 };
182
Simon Glassb2c1cac2014-02-26 15:59:21 -0700183 some-bus {
184 #address-cells = <1>;
185 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600186 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600187 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600188 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700189 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600190 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700191 compatible = "denx,u-boot-fdt-test";
192 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600193 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700194 ping-add = <5>;
195 };
Simon Glass40717422014-07-23 06:55:18 -0600196 c-test@0 {
197 compatible = "denx,u-boot-fdt-test";
198 reg = <0>;
199 ping-expect = <6>;
200 ping-add = <6>;
201 };
202 c-test@1 {
203 compatible = "denx,u-boot-fdt-test";
204 reg = <1>;
205 ping-expect = <7>;
206 ping-add = <7>;
207 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700208 };
209
210 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600211 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600212 ping-expect = <6>;
213 ping-add = <6>;
214 compatible = "google,another-fdt-test";
215 };
216
217 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600218 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600219 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700220 ping-add = <6>;
221 compatible = "google,another-fdt-test";
222 };
223
Simon Glass0ccb0972015-01-25 08:27:05 -0700224 f-test {
225 compatible = "denx,u-boot-fdt-test";
226 };
227
228 g-test {
229 compatible = "denx,u-boot-fdt-test";
230 };
231
Bin Mengd9d24782018-10-10 22:07:01 -0700232 h-test {
233 compatible = "denx,u-boot-fdt-test1";
234 };
235
developercf8bc132020-05-02 11:35:10 +0200236 i-test {
237 compatible = "mediatek,u-boot-fdt-test";
238 #address-cells = <1>;
239 #size-cells = <0>;
240
241 subnode@0 {
242 reg = <0>;
243 };
244
245 subnode@1 {
246 reg = <1>;
247 };
248
249 subnode@2 {
250 reg = <2>;
251 };
252 };
253
Simon Glass204675c2019-12-29 21:19:25 -0700254 devres-test {
255 compatible = "denx,u-boot-devres-test";
256 };
257
Simon Glass3c601b12020-07-07 13:12:06 -0600258 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600259 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600260 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600261 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600262 child {
263 compatible = "denx,u-boot-acpi-test";
264 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600265 };
266
Simon Glass3c601b12020-07-07 13:12:06 -0600267 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600268 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600269 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600270 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600271 };
272
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200273 clocks {
274 clk_fixed: clk-fixed {
275 compatible = "fixed-clock";
276 #clock-cells = <0>;
277 clock-frequency = <1234>;
278 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000279
280 clk_fixed_factor: clk-fixed-factor {
281 compatible = "fixed-factor-clock";
282 #clock-cells = <0>;
283 clock-div = <3>;
284 clock-mult = <2>;
285 clocks = <&clk_fixed>;
286 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200287
288 osc {
289 compatible = "fixed-clock";
290 #clock-cells = <0>;
291 clock-frequency = <20000000>;
292 };
Stephen Warrena9622432016-06-17 09:44:00 -0600293 };
294
295 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600296 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600297 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200298 assigned-clocks = <&clk_sandbox 3>;
299 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600300 };
301
302 clk-test {
303 compatible = "sandbox,clk-test";
304 clocks = <&clk_fixed>,
305 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200306 <&clk_sandbox 0>,
307 <&clk_sandbox 3>,
308 <&clk_sandbox 2>;
309 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600310 };
311
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200312 ccf: clk-ccf {
313 compatible = "sandbox,clk-ccf";
314 };
315
Simon Glass5b968632015-05-22 15:42:15 -0600316 eth@10002000 {
317 compatible = "sandbox,eth";
318 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500319 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600320 };
321
322 eth_5: eth@10003000 {
323 compatible = "sandbox,eth";
324 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500325 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600326 };
327
Bin Meng04a11cb2015-08-27 22:25:53 -0700328 eth_3: sbe5 {
329 compatible = "sandbox,eth";
330 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500331 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700332 };
333
Simon Glass5b968632015-05-22 15:42:15 -0600334 eth@10004000 {
335 compatible = "sandbox,eth";
336 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500337 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600338 };
339
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700340 firmware {
341 sandbox_firmware: sandbox-firmware {
342 compatible = "sandbox,firmware";
343 };
344 };
345
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100346 pinctrl-gpio {
347 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700348
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100349 gpio_a: base-gpios {
350 compatible = "sandbox,gpio";
351 gpio-controller;
352 #gpio-cells = <1>;
353 gpio-bank-name = "a";
354 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200355 hog_input_active_low {
356 gpio-hog;
357 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200358 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200359 };
360 hog_input_active_high {
361 gpio-hog;
362 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200363 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200364 };
365 hog_output_low {
366 gpio-hog;
367 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200368 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200369 };
370 hog_output_high {
371 gpio-hog;
372 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200373 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200374 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100375 };
376
377 gpio_b: extra-gpios {
378 compatible = "sandbox,gpio";
379 gpio-controller;
380 #gpio-cells = <5>;
381 gpio-bank-name = "b";
382 sandbox,gpio-count = <10>;
383 };
Simon Glass25348a42014-10-13 23:42:11 -0600384
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100385 gpio_c: pinmux-gpios {
386 compatible = "sandbox,gpio";
387 gpio-controller;
388 #gpio-cells = <2>;
389 gpio-bank-name = "c";
390 sandbox,gpio-count = <10>;
391 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100392 };
393
Simon Glass7df766e2014-12-10 08:55:55 -0700394 i2c@0 {
395 #address-cells = <1>;
396 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600397 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700398 compatible = "sandbox,i2c";
399 clock-frequency = <100000>;
400 eeprom@2c {
401 reg = <0x2c>;
402 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700403 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700404 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200405
Simon Glass336b2952015-05-22 15:42:17 -0600406 rtc_0: rtc@43 {
407 reg = <0x43>;
408 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700409 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600410 };
411
412 rtc_1: rtc@61 {
413 reg = <0x61>;
414 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700415 sandbox,emul = <&emul1>;
416 };
417
418 i2c_emul: emul {
419 reg = <0xff>;
420 compatible = "sandbox,i2c-emul-parent";
421 emul_eeprom: emul-eeprom {
422 compatible = "sandbox,i2c-eeprom";
423 sandbox,filename = "i2c.bin";
424 sandbox,size = <256>;
425 };
426 emul0: emul0 {
427 compatible = "sandbox,i2c-rtc";
428 };
429 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600430 compatible = "sandbox,i2c-rtc";
431 };
432 };
433
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200434 sandbox_pmic: sandbox_pmic {
435 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700436 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200437 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200438
439 mc34708: pmic@41 {
440 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700441 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200442 };
Simon Glass7df766e2014-12-10 08:55:55 -0700443 };
444
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100445 bootcount@0 {
446 compatible = "u-boot,bootcount-rtc";
447 rtc = <&rtc_1>;
448 offset = <0x13>;
449 };
450
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100451 adc@0 {
452 compatible = "sandbox,adc";
453 vdd-supply = <&buck2>;
454 vss-microvolts = <0>;
455 };
456
Simon Glass515dcff2020-02-06 09:55:00 -0700457 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700458 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700459 interrupt-controller;
460 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700461 };
462
Simon Glass90b6fef2016-01-18 19:52:26 -0700463 lcd {
464 u-boot,dm-pre-reloc;
465 compatible = "sandbox,lcd-sdl";
466 xres = <1366>;
467 yres = <768>;
468 };
469
Simon Glassd783eb32015-07-06 12:54:34 -0600470 leds {
471 compatible = "gpio-leds";
472
473 iracibble {
474 gpios = <&gpio_a 1 0>;
475 label = "sandbox:red";
476 };
477
478 martinet {
479 gpios = <&gpio_a 2 0>;
480 label = "sandbox:green";
481 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200482
483 default_on {
484 gpios = <&gpio_a 5 0>;
485 label = "sandbox:default_on";
486 default-state = "on";
487 };
488
489 default_off {
490 gpios = <&gpio_a 6 0>;
491 label = "sandbox:default_off";
492 default-state = "off";
493 };
Simon Glassd783eb32015-07-06 12:54:34 -0600494 };
495
Stephen Warren62f2c902016-05-16 17:41:37 -0600496 mbox: mbox {
497 compatible = "sandbox,mbox";
498 #mbox-cells = <1>;
499 };
500
501 mbox-test {
502 compatible = "sandbox,mbox-test";
503 mboxes = <&mbox 100>, <&mbox 1>;
504 mbox-names = "other", "test";
505 };
506
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900507 cpus {
508 cpu-test1 {
509 compatible = "sandbox,cpu_sandbox";
510 u-boot,dm-pre-reloc;
511 };
Mario Sixdea5df72018-08-06 10:23:44 +0200512
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900513 cpu-test2 {
514 compatible = "sandbox,cpu_sandbox";
515 u-boot,dm-pre-reloc;
516 };
Mario Sixdea5df72018-08-06 10:23:44 +0200517
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900518 cpu-test3 {
519 compatible = "sandbox,cpu_sandbox";
520 u-boot,dm-pre-reloc;
521 };
Mario Sixdea5df72018-08-06 10:23:44 +0200522 };
523
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500524 chipid: chipid {
525 compatible = "sandbox,soc";
526 };
527
Simon Glassc953aaf2018-12-10 10:37:34 -0700528 i2s: i2s {
529 compatible = "sandbox,i2s";
530 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700531 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700532 };
533
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200534 nop-test_0 {
535 compatible = "sandbox,nop_sandbox1";
536 nop-test_1 {
537 compatible = "sandbox,nop_sandbox2";
538 bind = "True";
539 };
540 nop-test_2 {
541 compatible = "sandbox,nop_sandbox2";
542 bind = "False";
543 };
544 };
545
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200546 misc-test {
547 compatible = "sandbox,misc_sandbox";
548 };
549
Simon Glasse4fef742017-04-23 20:02:07 -0600550 mmc2 {
551 compatible = "sandbox,mmc";
552 };
553
554 mmc1 {
555 compatible = "sandbox,mmc";
556 };
557
558 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600559 compatible = "sandbox,mmc";
560 };
561
Simon Glass53a68b32019-02-16 20:24:50 -0700562 pch {
563 compatible = "sandbox,pch";
564 };
565
Tom Rini4a3ca482020-02-11 12:41:23 -0500566 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700567 compatible = "sandbox,pci";
568 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500569 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700570 #address-cells = <3>;
571 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600572 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700573 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700574 pci@0,0 {
575 compatible = "pci-generic";
576 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600577 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700578 };
Alex Margineanf1274432019-06-07 11:24:24 +0300579 pci@1,0 {
580 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600581 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
582 reg = <0x02000814 0 0 0 0
583 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600584 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300585 };
Simon Glass937bb472019-12-06 21:41:57 -0700586 p2sb-pci@2,0 {
587 compatible = "sandbox,p2sb";
588 reg = <0x02001010 0 0 0 0>;
589 sandbox,emul = <&p2sb_emul>;
590
591 adder {
592 intel,p2sb-port-id = <3>;
593 compatible = "sandbox,adder";
594 };
595 };
Simon Glass8c501022019-12-06 21:41:54 -0700596 pci@1e,0 {
597 compatible = "sandbox,pmc";
598 reg = <0xf000 0 0 0 0>;
599 sandbox,emul = <&pmc_emul1e>;
600 acpi-base = <0x400>;
601 gpe0-dwx-mask = <0xf>;
602 gpe0-dwx-shift-base = <4>;
603 gpe0-dw = <6 7 9>;
604 gpe0-sts = <0x20>;
605 gpe0-en = <0x30>;
606 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700607 pci@1f,0 {
608 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600609 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
610 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600611 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700612 };
613 };
614
Simon Glassb98ba4c2019-09-25 08:56:10 -0600615 pci-emul0 {
616 compatible = "sandbox,pci-emul-parent";
617 swap_case_emul0_0: emul0@0,0 {
618 compatible = "sandbox,swap-case";
619 };
620 swap_case_emul0_1: emul0@1,0 {
621 compatible = "sandbox,swap-case";
622 use-ea;
623 };
624 swap_case_emul0_1f: emul0@1f,0 {
625 compatible = "sandbox,swap-case";
626 };
Simon Glass937bb472019-12-06 21:41:57 -0700627 p2sb_emul: emul@2,0 {
628 compatible = "sandbox,p2sb-emul";
629 };
Simon Glass8c501022019-12-06 21:41:54 -0700630 pmc_emul1e: emul@1e,0 {
631 compatible = "sandbox,pmc-emul";
632 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600633 };
634
Tom Rini4a3ca482020-02-11 12:41:23 -0500635 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700636 compatible = "sandbox,pci";
637 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500638 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700639 #address-cells = <3>;
640 #size-cells = <2>;
641 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
642 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700643 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200644 0x0c 0x00 0x1234 0x5678
645 0x10 0x00 0x1234 0x5678>;
646 pci@10,0 {
647 reg = <0x8000 0 0 0 0>;
648 };
Bin Meng408e5902018-08-03 01:14:41 -0700649 };
650
Tom Rini4a3ca482020-02-11 12:41:23 -0500651 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700652 compatible = "sandbox,pci";
653 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500654 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700655 #address-cells = <3>;
656 #size-cells = <2>;
657 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
658 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
659 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
660 pci@1f,0 {
661 compatible = "pci-generic";
662 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600663 sandbox,emul = <&swap_case_emul2_1f>;
664 };
665 };
666
667 pci-emul2 {
668 compatible = "sandbox,pci-emul-parent";
669 swap_case_emul2_1f: emul2@1f,0 {
670 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700671 };
672 };
673
Ramon Friedc64f19b2019-04-27 11:15:23 +0300674 pci_ep: pci_ep {
675 compatible = "sandbox,pci_ep";
676 };
677
Simon Glass9c433fe2017-04-23 20:10:44 -0600678 probing {
679 compatible = "simple-bus";
680 test1 {
681 compatible = "denx,u-boot-probe-test";
682 };
683
684 test2 {
685 compatible = "denx,u-boot-probe-test";
686 };
687
688 test3 {
689 compatible = "denx,u-boot-probe-test";
690 };
691
692 test4 {
693 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100694 first-syscon = <&syscon0>;
695 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100696 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600697 };
698 };
699
Stephen Warren92c67fa2016-07-13 13:45:31 -0600700 pwrdom: power-domain {
701 compatible = "sandbox,power-domain";
702 #power-domain-cells = <1>;
703 };
704
705 power-domain-test {
706 compatible = "sandbox,power-domain-test";
707 power-domains = <&pwrdom 2>;
708 };
709
Simon Glass5620cf82018-10-01 12:22:40 -0600710 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600711 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600712 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600713 };
714
715 pwm2 {
716 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600717 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600718 };
719
Simon Glass3d355e62015-07-06 12:54:31 -0600720 ram {
721 compatible = "sandbox,ram";
722 };
723
Simon Glassd860f222015-07-06 12:54:29 -0600724 reset@0 {
725 compatible = "sandbox,warm-reset";
726 };
727
728 reset@1 {
729 compatible = "sandbox,reset";
730 };
731
Stephen Warren6488e642016-06-17 09:43:59 -0600732 resetc: reset-ctl {
733 compatible = "sandbox,reset-ctl";
734 #reset-cells = <1>;
735 };
736
737 reset-ctl-test {
738 compatible = "sandbox,reset-ctl-test";
739 resets = <&resetc 100>, <&resetc 2>;
740 reset-names = "other", "test";
741 };
742
Sughosh Ganu23e37512019-12-28 23:58:31 +0530743 rng {
744 compatible = "sandbox,sandbox-rng";
745 };
746
Nishanth Menonedf85812015-09-17 15:42:41 -0500747 rproc_1: rproc@1 {
748 compatible = "sandbox,test-processor";
749 remoteproc-name = "remoteproc-test-dev1";
750 };
751
752 rproc_2: rproc@2 {
753 compatible = "sandbox,test-processor";
754 internal-memory-mapped;
755 remoteproc-name = "remoteproc-test-dev2";
756 };
757
Simon Glass5620cf82018-10-01 12:22:40 -0600758 panel {
759 compatible = "simple-panel";
760 backlight = <&backlight 0 100>;
761 };
762
Ramon Fried26ed32e2018-07-02 02:57:59 +0300763 smem@0 {
764 compatible = "sandbox,smem";
765 };
766
Simon Glass76072ac2018-12-10 10:37:36 -0700767 sound {
768 compatible = "sandbox,sound";
769 cpu {
770 sound-dai = <&i2s 0>;
771 };
772
773 codec {
774 sound-dai = <&audio 0>;
775 };
776 };
777
Simon Glass25348a42014-10-13 23:42:11 -0600778 spi@0 {
779 #address-cells = <1>;
780 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600781 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600782 compatible = "sandbox,spi";
783 cs-gpios = <0>, <&gpio_a 0>;
784 spi.bin@0 {
785 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000786 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600787 spi-max-frequency = <40000000>;
788 sandbox,filename = "spi.bin";
789 };
790 };
791
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100792 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600793 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200794 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600795 };
796
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100797 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600798 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600799 reg = <0x20 5
800 0x28 6
801 0x30 7
802 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600803 };
804
Patrick Delaunayee010432019-03-07 09:57:13 +0100805 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900806 compatible = "simple-mfd", "syscon";
807 reg = <0x40 5
808 0x48 6
809 0x50 7
810 0x58 8>;
811 };
812
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800813 timer {
814 compatible = "sandbox,timer";
815 clock-frequency = <1000000>;
816 };
817
Miquel Raynal80938c12018-05-15 11:57:27 +0200818 tpm2 {
819 compatible = "sandbox,tpm2";
820 };
821
Simon Glass5b968632015-05-22 15:42:15 -0600822 uart0: serial {
823 compatible = "sandbox,serial";
824 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500825 };
826
Simon Glass31680482015-03-25 12:23:05 -0600827 usb_0: usb@0 {
828 compatible = "sandbox,usb";
829 status = "disabled";
830 hub {
831 compatible = "sandbox,usb-hub";
832 #address-cells = <1>;
833 #size-cells = <0>;
834 flash-stick {
835 reg = <0>;
836 compatible = "sandbox,usb-flash";
837 };
838 };
839 };
840
841 usb_1: usb@1 {
842 compatible = "sandbox,usb";
843 hub {
844 compatible = "usb-hub";
845 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +0200846 #address-cells = <1>;
847 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -0600848 hub-emul {
849 compatible = "sandbox,usb-hub";
850 #address-cells = <1>;
851 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700852 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600853 reg = <0>;
854 compatible = "sandbox,usb-flash";
855 sandbox,filepath = "testflash.bin";
856 };
857
Simon Glass4700fe52015-11-08 23:48:01 -0700858 flash-stick@1 {
859 reg = <1>;
860 compatible = "sandbox,usb-flash";
861 sandbox,filepath = "testflash1.bin";
862 };
863
864 flash-stick@2 {
865 reg = <2>;
866 compatible = "sandbox,usb-flash";
867 sandbox,filepath = "testflash2.bin";
868 };
869
Simon Glassc0ccc722015-11-08 23:48:08 -0700870 keyb@3 {
871 reg = <3>;
872 compatible = "sandbox,usb-keyb";
873 };
874
Simon Glass31680482015-03-25 12:23:05 -0600875 };
Michael Walle7c961322020-06-02 01:47:07 +0200876
877 usbstor@1 {
878 reg = <1>;
879 };
880 usbstor@3 {
881 reg = <3>;
882 };
Simon Glass31680482015-03-25 12:23:05 -0600883 };
884 };
885
886 usb_2: usb@2 {
887 compatible = "sandbox,usb";
888 status = "disabled";
889 };
890
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200891 spmi: spmi@0 {
892 compatible = "sandbox,spmi";
893 #address-cells = <0x1>;
894 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600895 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200896 pm8916@0 {
897 compatible = "qcom,spmi-pmic";
898 reg = <0x0 0x1>;
899 #address-cells = <0x1>;
900 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600901 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200902
903 spmi_gpios: gpios@c000 {
904 compatible = "qcom,pm8916-gpio";
905 reg = <0xc000 0x400>;
906 gpio-controller;
907 gpio-count = <4>;
908 #gpio-cells = <2>;
909 gpio-bank-name="spmi";
910 };
911 };
912 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700913
914 wdt0: wdt@0 {
915 compatible = "sandbox,wdt";
916 };
Rob Clarka471b672018-01-10 11:33:30 +0100917
Mario Six95922152018-08-09 14:51:19 +0200918 axi: axi@0 {
919 compatible = "sandbox,axi";
920 #address-cells = <0x1>;
921 #size-cells = <0x1>;
922 store@0 {
923 compatible = "sandbox,sandbox_store";
924 reg = <0x0 0x400>;
925 };
926 };
927
Rob Clarka471b672018-01-10 11:33:30 +0100928 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700929 #address-cells = <1>;
930 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -0700931 setting = "sunrise ohoka";
932 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -0700933 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -0600934 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +0100935 chosen-test {
936 compatible = "denx,u-boot-fdt-test";
937 reg = <9 1>;
938 };
939 };
Mario Six35616ef2018-03-12 14:53:33 +0100940
941 translation-test@8000 {
942 compatible = "simple-bus";
943 reg = <0x8000 0x4000>;
944
945 #address-cells = <0x2>;
946 #size-cells = <0x1>;
947
948 ranges = <0 0x0 0x8000 0x1000
949 1 0x100 0x9000 0x1000
950 2 0x200 0xA000 0x1000
951 3 0x300 0xB000 0x1000
952 >;
953
Fabien Dessenne22236e02019-05-31 15:11:30 +0200954 dma-ranges = <0 0x000 0x10000000 0x1000
955 1 0x100 0x20000000 0x1000
956 >;
957
Mario Six35616ef2018-03-12 14:53:33 +0100958 dev@0,0 {
959 compatible = "denx,u-boot-fdt-dummy";
960 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100961 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100962 };
963
964 dev@1,100 {
965 compatible = "denx,u-boot-fdt-dummy";
966 reg = <1 0x100 0x1000>;
967
968 };
969
970 dev@2,200 {
971 compatible = "denx,u-boot-fdt-dummy";
972 reg = <2 0x200 0x1000>;
973 };
974
975
976 noxlatebus@3,300 {
977 compatible = "simple-bus";
978 reg = <3 0x300 0x1000>;
979
980 #address-cells = <0x1>;
981 #size-cells = <0x0>;
982
983 dev@42 {
984 compatible = "denx,u-boot-fdt-dummy";
985 reg = <0x42>;
986 };
987 };
988 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200989
990 osd {
991 compatible = "sandbox,sandbox_osd";
992 };
Tom Rinib93eea72018-09-30 18:16:51 -0400993
Mario Sixab664ff2018-07-31 11:44:13 +0200994 board {
995 compatible = "sandbox,board_sandbox";
996 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200997
998 sandbox_tee {
999 compatible = "sandbox,tee";
1000 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001001
1002 sandbox_virtio1 {
1003 compatible = "sandbox,virtio1";
1004 };
1005
1006 sandbox_virtio2 {
1007 compatible = "sandbox,virtio2";
1008 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001009
1010 pinctrl {
1011 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001012
1013 pinctrl-names = "default";
1014 pinctrl-0 = <&gpios>;
1015
1016 gpios: gpios {
1017 gpio0 {
1018 pins = "GPIO0";
1019 bias-pull-up;
1020 input-disable;
1021 };
1022 gpio1 {
1023 pins = "GPIO1";
1024 output-high;
1025 drive-open-drain;
1026 };
1027 gpio2 {
1028 pins = "GPIO2";
1029 bias-pull-down;
1030 input-enable;
1031 };
1032 gpio3 {
1033 pins = "GPIO3";
1034 bias-disable;
1035 };
1036 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001037 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001038
1039 hwspinlock@0 {
1040 compatible = "sandbox,hwspinlock";
1041 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001042
1043 dma: dma {
1044 compatible = "sandbox,dma";
1045 #dma-cells = <1>;
1046
1047 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1048 dma-names = "m2m", "tx0", "rx0";
1049 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001050
Alex Marginean0649be52019-07-12 10:13:53 +03001051 /*
1052 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1053 * end of the test. If parent mdio is removed first, clean-up of the
1054 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1055 * active at the end of the test. That it turn doesn't allow the mdio
1056 * class to be destroyed, triggering an error.
1057 */
1058 mdio-mux-test {
1059 compatible = "sandbox,mdio-mux";
1060 #address-cells = <1>;
1061 #size-cells = <0>;
1062 mdio-parent-bus = <&mdio>;
1063
1064 mdio-ch-test@0 {
1065 reg = <0>;
1066 };
1067 mdio-ch-test@1 {
1068 reg = <1>;
1069 };
1070 };
1071
1072 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001073 compatible = "sandbox,mdio";
1074 };
Sean Andersonb7860542020-06-24 06:41:12 -04001075
1076 pm-bus-test {
1077 compatible = "simple-pm-bus";
1078 clocks = <&clk_sandbox 4>;
1079 power-domains = <&pwrdom 1>;
1080 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001081
1082 resetc2: syscon-reset {
1083 compatible = "syscon-reset";
1084 #reset-cells = <1>;
1085 regmap = <&syscon0>;
1086 offset = <1>;
1087 mask = <0x27FFFFFF>;
1088 assert-high = <0>;
1089 };
1090
1091 syscon-reset-test {
1092 compatible = "sandbox,misc_sandbox";
1093 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1094 reset-names = "valid", "no_mask", "out_of_range";
1095 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001096};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001097
1098#include "sandbox_pmic.dtsi"