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git01.mediatek.com / filogic / uboot / a5579ca1a7c40d9ea5ed3a6889a3ffd287a9b7b9 / . / drivers / serial / serial_sh.h
blob: df21b37a8df634ab718326c377f4831bf33d49e8 [file] [log] [blame]
Nobuhiro Iwamatsua5579ca2010-10-26 03:55:15 +0900[diff] [blame^]1/*
2 * Copy and modify from linux/drivers/serial/sh-sci.h
3 */
4
5struct uart_port {
6 unsigned long iobase; /* in/out[bwl] */
7 unsigned char *membase; /* read/write[bwl] */
8 unsigned long mapbase; /* for ioremap */
9 unsigned int type; /* port type */
10};
11
12#define PORT_SCI 52
13#define PORT_SCIF 53
14#define PORT_SCIFA 83
15#define PORT_SCIFB 93
16
17#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
18#include <asm/regs306x.h>
19#endif
20#if defined(CONFIG_H8S2678)
21#include <asm/regs267x.h>
22#endif
23
24#if defined(CONFIG_CPU_SH7706) || \
25 defined(CONFIG_CPU_SH7707) || \
26 defined(CONFIG_CPU_SH7708) || \
27 defined(CONFIG_CPU_SH7709)
28# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
29# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
30# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
31#elif defined(CONFIG_CPU_SH7705)
32# define SCIF0 0xA4400000
33# define SCIF2 0xA4410000
34# define SCSMR_Ir 0xA44A0000
35# define IRDA_SCIF SCIF0
36# define SCPCR 0xA4000116
37# define SCPDR 0xA4000136
38
39/* Set the clock source,
40 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
41 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
42 */
43# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
44#elif defined(CONFIG_CPU_SH7720) || \
45 defined(CONFIG_CPU_SH7721) || \
46 defined(CONFIG_ARCH_SH7367) || \
47 defined(CONFIG_ARCH_SH7377) || \
48 defined(CONFIG_ARCH_SH7372)
49# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
50# define PORT_PTCR 0xA405011EUL
51# define PORT_PVCR 0xA4050122UL
52# define SCIF_ORER 0x0200 /* overrun error bit */
53#elif defined(CONFIG_SH_RTS7751R2D)
54# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
55# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
56# define SCIF_ORER 0x0001 /* overrun error bit */
57# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
58#elif defined(CONFIG_CPU_SH7750) || \
59 defined(CONFIG_CPU_SH7750R) || \
60 defined(CONFIG_CPU_SH7750S) || \
61 defined(CONFIG_CPU_SH7091) || \
62 defined(CONFIG_CPU_SH7751) || \
63 defined(CONFIG_CPU_SH7751R)
64# define SCSPTR1 0xffe0001c /* 8 bit SCI */
65# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
66# define SCIF_ORER 0x0001 /* overrun error bit */
67# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
68 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
69 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
70#elif defined(CONFIG_CPU_SH7760)
71# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
72# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
73# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
74# define SCIF_ORER 0x0001 /* overrun error bit */
75# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
76#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
77# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
78# define SCIF_ORER 0x0001 /* overrun error bit */
79# define PACR 0xa4050100
80# define PBCR 0xa4050102
81# define SCSCR_INIT(port) 0x3B
82#elif defined(CONFIG_CPU_SH7343)
83# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
84# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
85# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
86# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
87# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
88#elif defined(CONFIG_CPU_SH7722)
89# define PADR 0xA4050120
90# define PSDR 0xA405013e
91# define PWDR 0xA4050166
92# define PSCR 0xA405011E
93# define SCIF_ORER 0x0001 /* overrun error bit */
94# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
95#elif defined(CONFIG_CPU_SH7366)
96# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
97# define SCSPTR0 SCPDR0
98# define SCIF_ORER 0x0001 /* overrun error bit */
99# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
100#elif defined(CONFIG_CPU_SH7723)
101# define SCSPTR0 0xa4050160
102# define SCSPTR1 0xa405013e
103# define SCSPTR2 0xa4050160
104# define SCSPTR3 0xa405013e
105# define SCSPTR4 0xa4050128
106# define SCSPTR5 0xa4050128
107# define SCIF_ORER 0x0001 /* overrun error bit */
108# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
109#elif defined(CONFIG_CPU_SH7724)
110# define SCIF_ORER 0x0001 /* overrun error bit */
111# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
112 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
113 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
114#elif defined(CONFIG_CPU_SH4_202)
115# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
116# define SCIF_ORER 0x0001 /* overrun error bit */
117# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
118#elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
119# define SCIF_BASE_ADDR 0x01030000
120# define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
121# define SCIF_PTR2_OFFS 0x0000020
122# define SCIF_LSR2_OFFS 0x0000024
123# define SCSPTR\
124 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
125# define SCLSR2\
126 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
127# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
128#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
129# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
130# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
131#elif defined(CONFIG_H8S2678)
132# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
133# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
134#elif defined(CONFIG_CPU_SH7757)
135# define SCSPTR0 0xfe4b0020
136# define SCSPTR1 0xfe4b0020
137# define SCSPTR2 0xfe4b0020
138# define SCIF_ORER 0x0001
139# define SCSCR_INIT(port) 0x38
140# define SCIF_ONLY
141#elif defined(CONFIG_CPU_SH7763)
142# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
143# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
144# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
145# define SCIF_ORER 0x0001 /* overrun error bit */
146# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
147#elif defined(CONFIG_CPU_SH7770)
148# define SCSPTR0 0xff923020 /* 16 bit SCIF */
149# define SCSPTR1 0xff924020 /* 16 bit SCIF */
150# define SCSPTR2 0xff925020 /* 16 bit SCIF */
151# define SCIF_ORER 0x0001 /* overrun error bit */
152# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
153#elif defined(CONFIG_CPU_SH7780)
154# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
155# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
156# define SCIF_ORER 0x0001 /* Overrun error bit */
157
158#if defined(CONFIG_SH_SH2007)
159/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
160# define SCSCR_INIT(port) 0x38
161#else
162/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
163# define SCSCR_INIT(port) 0x3a
164#endif
165
166#elif defined(CONFIG_CPU_SH7785) || \
167 defined(CONFIG_CPU_SH7786)
168# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
169# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
170# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
171# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
172# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
173# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
174# define SCIF_ORER 0x0001 /* Overrun error bit */
175# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
176#elif defined(CONFIG_CPU_SH7201) || \
177 defined(CONFIG_CPU_SH7203) || \
178 defined(CONFIG_CPU_SH7206) || \
179 defined(CONFIG_CPU_SH7263)
180# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
181# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
182# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
183# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
184# if defined(CONFIG_CPU_SH7201)
185# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
186# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
187# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
188# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
189# endif
190# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
191#elif defined(CONFIG_CPU_SH7619)
192# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
193# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
194# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
195# define SCIF_ORER 0x0001 /* overrun error bit */
196# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
197#elif defined(CONFIG_CPU_SHX3)
198# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
199# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
200# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
201# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
202# define SCIF_ORER 0x0001 /* Overrun error bit */
203# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
204#else
205# error CPU subtype not defined
206#endif
207
208/* SCSCR */
209#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
210#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
211#define SCI_CTRL_FLAGS_TE 0x20 /* all */
212#define SCI_CTRL_FLAGS_RE 0x10 /* all */
213#if defined(CONFIG_CPU_SH7750) || \
214 defined(CONFIG_CPU_SH7091) || \
215 defined(CONFIG_CPU_SH7750R) || \
216 defined(CONFIG_CPU_SH7722) || \
217 defined(CONFIG_CPU_SH7750S) || \
218 defined(CONFIG_CPU_SH7751) || \
219 defined(CONFIG_CPU_SH7751R) || \
220 defined(CONFIG_CPU_SH7763) || \
221 defined(CONFIG_CPU_SH7780) || \
222 defined(CONFIG_CPU_SH7785) || \
223 defined(CONFIG_CPU_SH7786) || \
224 defined(CONFIG_CPU_SHX3)
225#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
226#elif defined(CONFIG_CPU_SH7724)
227#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
228#else
229#define SCI_CTRL_FLAGS_REIE 0
230#endif
231/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
232/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
233/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
234/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
235
236/* SCxSR SCI */
237#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
238#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
239#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
240#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
241#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
242#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
243/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
244/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
245
246#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
247
248/* SCxSR SCIF */
249#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
250#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
251#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
252#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
253#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
254#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
255#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
256#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
257
258#if defined(CONFIG_CPU_SH7705) || \
259 defined(CONFIG_CPU_SH7720) || \
260 defined(CONFIG_CPU_SH7721) || \
261 defined(CONFIG_ARCH_SH7367) || \
262 defined(CONFIG_ARCH_SH7377) || \
263 defined(CONFIG_ARCH_SH7372)
264# define SCIF_ORER 0x0200
265# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
266# define SCIF_RFDC_MASK 0x007f
267# define SCIF_TXROOM_MAX 64
268#elif defined(CONFIG_CPU_SH7763)
269# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
270# define SCIF_RFDC_MASK 0x007f
271# define SCIF_TXROOM_MAX 64
272/* SH7763 SCIF2 support */
273# define SCIF2_RFDC_MASK 0x001f
274# define SCIF2_TXROOM_MAX 16
275#else
276# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
277# define SCIF_RFDC_MASK 0x001f
278# define SCIF_TXROOM_MAX 16
279#endif
280
281#ifndef SCIF_ORER
282#define SCIF_ORER 0x0000
283#endif
284
285#define SCxSR_TEND(port)\
286 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
287#define SCxSR_ERRORS(port)\
288 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
289#define SCxSR_RDxF(port)\
290 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
291#define SCxSR_TDxE(port)\
292 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
293#define SCxSR_FER(port)\
294 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
295#define SCxSR_PER(port)\
296 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
297#define SCxSR_BRK(port)\
298 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
299#define SCxSR_ORER(port)\
300 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
301
302#if defined(CONFIG_CPU_SH7705) || \
303 defined(CONFIG_CPU_SH7720) || \
304 defined(CONFIG_CPU_SH7721) || \
305 defined(CONFIG_ARCH_SH7367) || \
306 defined(CONFIG_ARCH_SH7377) || \
307 defined(CONFIG_ARCH_SH7372)
308# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
309# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
310# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
311# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
312#else
313# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
314# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
315# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
316# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
317#endif
318
319/* SCFCR */
320#define SCFCR_RFRST 0x0002
321#define SCFCR_TFRST 0x0004
322#define SCFCR_TCRST 0x4000
323#define SCFCR_MCE 0x0008
324
325#define SCI_MAJOR 204
326#define SCI_MINOR_START 8
327
328/* Generic serial flags */
329#define SCI_RX_THROTTLE 0x0000001
330
331#define SCI_MAGIC 0xbabeface
332
333/*
334 * Events are used to schedule things to happen at timer-interrupt
335 * time, instead of at rs interrupt time.
336 */
337#define SCI_EVENT_WRITE_WAKEUP 0
338
339#define SCI_IN(size, offset)\
340 if ((size) == 8) {\
341 return readb(port->membase + (offset));\
342 } else {\
343 return readw(port->membase + (offset));\
344 }
345#define SCI_OUT(size, offset, value)\
346 if ((size) == 8) {\
347 writeb(value, port->membase + (offset));\
348 } else if ((size) == 16) {\
349 writew(value, port->membase + (offset));\
350 }
351
352#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
353 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
354 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
355 SCI_IN(scif_size, scif_offset)\
356 } else { /* PORT_SCI or PORT_SCIFA */\
357 SCI_IN(sci_size, sci_offset);\
358 }\
359 }\
360static inline void sci_##name##_out(struct uart_port *port,\
361 unsigned int value) {\
362 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
363 SCI_OUT(scif_size, scif_offset, value)\
364 } else { /* PORT_SCI or PORT_SCIFA */\
365 SCI_OUT(sci_size, sci_offset, value);\
366 }\
367}
368
369#ifdef CONFIG_H8300
370/* h8300 don't have SCIF */
371#define CPU_SCIF_FNS(name) \
372 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
373 return 0;\
374 }\
375 static inline void sci_##name##_out(struct uart_port *port,\
376 unsigned int value) {\
377 }
378#else
379#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
380 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
381 SCI_IN(scif_size, scif_offset);\
382 }\
383 static inline void sci_##name##_out(struct uart_port *port,\
384 unsigned int value) {\
385 SCI_OUT(scif_size, scif_offset, value);\
386 }
387#endif
388
389#define CPU_SCI_FNS(name, sci_offset, sci_size)\
390 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
391 SCI_IN(sci_size, sci_offset);\
392 }\
393 static inline void sci_##name##_out(struct uart_port *port,\
394 unsigned int value) {\
395 SCI_OUT(sci_size, sci_offset, value);\
396 }
397
398#if defined(CONFIG_SH3) || \
399 defined(CONFIG_ARCH_SH7367) || \
400 defined(CONFIG_ARCH_SH7377) || \
401 defined(CONFIG_ARCH_SH7372)
402#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
403#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
404 sh4_sci_offset, sh4_sci_size, \
405 sh3_scif_offset, sh3_scif_size, \
406 sh4_scif_offset, sh4_scif_size, \
407 h8_sci_offset, h8_sci_size) \
408 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
409 sh4_scif_offset, sh4_scif_size)
410#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
411 sh4_scif_offset, sh4_scif_size) \
412 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
413#elif defined(CONFIG_CPU_SH7705) || \
414 defined(CONFIG_CPU_SH7720) || \
415 defined(CONFIG_CPU_SH7721) || \
416 defined(CONFIG_ARCH_SH7367) || \
417 defined(CONFIG_ARCH_SH7377)
418#define SCIF_FNS(name, scif_offset, scif_size) \
419 CPU_SCIF_FNS(name, scif_offset, scif_size)
420#elif defined(CONFIG_ARCH_SH7372)
421#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
422 sh4_scifb_offset, sh4_scifb_size) \
423 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
424 sh4_scifb_offset, sh4_scifb_size)
425#define SCIF_FNS(name, scif_offset, scif_size) \
426 CPU_SCIF_FNS(name, scif_offset, scif_size)
427#else
428#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
429 sh4_sci_offset, sh4_sci_size, \
430 sh3_scif_offset, sh3_scif_size,\
431 sh4_scif_offset, sh4_scif_size, \
432 h8_sci_offset, h8_sci_size) \
433 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
434 sh3_scif_offset, sh3_scif_size)
435#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
436 sh4_scif_offset, sh4_scif_size) \
437 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
438#endif
439#elif defined(__H8300H__) || defined(__H8300S__)
440#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
441 sh4_sci_offset, sh4_sci_size, \
442 sh3_scif_offset, sh3_scif_size,\
443 sh4_scif_offset, sh4_scif_size, \
444 h8_sci_offset, h8_sci_size) \
445 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
446#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
447 sh4_scif_offset, sh4_scif_size) \
448 CPU_SCIF_FNS(name)
449#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
450 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
451 sh4_scif_offset, sh4_scif_size) \
452 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
453 sh4_scif_offset, sh4_scif_size)
454 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
455 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
456#else
457#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
458 sh4_sci_offset, sh4_sci_size, \
459 sh3_scif_offset, sh3_scif_size,\
460 sh4_scif_offset, sh4_scif_size, \
461 h8_sci_offset, h8_sci_size) \
462 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
463 sh4_scif_offset, sh4_scif_size)
464#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
465 sh4_scif_offset, sh4_scif_size) \
466 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
467#endif
468
469#if defined(CONFIG_CPU_SH7705) || \
470 defined(CONFIG_CPU_SH7720) || \
471 defined(CONFIG_CPU_SH7721) || \
472 defined(CONFIG_ARCH_SH7367) || \
473 defined(CONFIG_ARCH_SH7377)
474
475SCIF_FNS(SCSMR, 0x00, 16)
476SCIF_FNS(SCBRR, 0x04, 8)
477SCIF_FNS(SCSCR, 0x08, 16)
478SCIF_FNS(SCTDSR, 0x0c, 8)
479SCIF_FNS(SCFER, 0x10, 16)
480SCIF_FNS(SCxSR, 0x14, 16)
481SCIF_FNS(SCFCR, 0x18, 16)
482SCIF_FNS(SCFDR, 0x1c, 16)
483SCIF_FNS(SCxTDR, 0x20, 8)
484SCIF_FNS(SCxRDR, 0x24, 8)
485SCIF_FNS(SCLSR, 0x00, 0)
486#elif defined(CONFIG_ARCH_SH7372)
487SCIF_FNS(SCSMR, 0x00, 16)
488SCIF_FNS(SCBRR, 0x04, 8)
489SCIF_FNS(SCSCR, 0x08, 16)
490SCIF_FNS(SCTDSR, 0x0c, 16)
491SCIF_FNS(SCFER, 0x10, 16)
492SCIF_FNS(SCxSR, 0x14, 16)
493SCIF_FNS(SCFCR, 0x18, 16)
494SCIF_FNS(SCFDR, 0x1c, 16)
495SCIF_FNS(SCTFDR, 0x38, 16)
496SCIF_FNS(SCRFDR, 0x3c, 16)
497SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
498SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
499SCIF_FNS(SCLSR, 0x00, 0)
500#elif defined(CONFIG_CPU_SH7723) ||\
501 defined(CONFIG_CPU_SH7724)
502SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
503SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
504SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
505SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
506SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
507SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
508SCIx_FNS(SCSPTR, 0, 0, 0, 0)
509SCIF_FNS(SCTDSR, 0x0c, 8)
510SCIF_FNS(SCFER, 0x10, 16)
511SCIF_FNS(SCFCR, 0x18, 16)
512SCIF_FNS(SCFDR, 0x1c, 16)
513SCIF_FNS(SCLSR, 0x24, 16)
514#else
515/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
516/* name off sz off sz off sz off sz off sz*/
517SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
518SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
519SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
520SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
521SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
522SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
523SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
524#if defined(CONFIG_CPU_SH7760) || \
525 defined(CONFIG_CPU_SH7780) || \
526 defined(CONFIG_CPU_SH7785) || \
527 defined(CONFIG_CPU_SH7786)
528SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
529SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
530SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
531SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
532SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
533#elif defined(CONFIG_CPU_SH7763)
534SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
535SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
536SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
537SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
538SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
539SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
540SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
541#else
542SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
543#if defined(CONFIG_CPU_SH7722)
544SCIF_FNS(SCSPTR, 0, 0, 0, 0)
545#else
546SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
547#endif
548SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
549#endif
550#endif
551#define sci_in(port, reg) sci_##reg##_in(port)
552#define sci_out(port, reg, value) sci_##reg##_out(port, value)
553
554/* H8/300 series SCI pins assignment */
555#if defined(__H8300H__) || defined(__H8300S__)
556static const struct __attribute__((packed)) {
557 int port; /* GPIO port no */
558 unsigned short rx, tx; /* GPIO bit no */
559} h8300_sci_pins[] = {
560#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
561 { /* SCI0 */
562 .port = H8300_GPIO_P9,
563 .rx = H8300_GPIO_B2,
564 .tx = H8300_GPIO_B0,
565 },
566 { /* SCI1 */
567 .port = H8300_GPIO_P9,
568 .rx = H8300_GPIO_B3,
569 .tx = H8300_GPIO_B1,
570 },
571 { /* SCI2 */
572 .port = H8300_GPIO_PB,
573 .rx = H8300_GPIO_B7,
574 .tx = H8300_GPIO_B6,
575 }
576#elif defined(CONFIG_H8S2678)
577 { /* SCI0 */
578 .port = H8300_GPIO_P3,
579 .rx = H8300_GPIO_B2,
580 .tx = H8300_GPIO_B0,
581 },
582 { /* SCI1 */
583 .port = H8300_GPIO_P3,
584 .rx = H8300_GPIO_B3,
585 .tx = H8300_GPIO_B1,
586 },
587 { /* SCI2 */
588 .port = H8300_GPIO_P5,
589 .rx = H8300_GPIO_B1,
590 .tx = H8300_GPIO_B0,
591 }
592#endif
593};
594#endif
595
596#if defined(CONFIG_CPU_SH7706) || \
597 defined(CONFIG_CPU_SH7707) || \
598 defined(CONFIG_CPU_SH7708) || \
599 defined(CONFIG_CPU_SH7709)
600static inline int sci_rxd_in(struct uart_port *port)
601{
602 if (port->mapbase == 0xfffffe80)
603 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
604 return 1;
605}
606#elif defined(CONFIG_CPU_SH7750) || \
607 defined(CONFIG_CPU_SH7751) || \
608 defined(CONFIG_CPU_SH7751R) || \
609 defined(CONFIG_CPU_SH7750R) || \
610 defined(CONFIG_CPU_SH7750S) || \
611 defined(CONFIG_CPU_SH7091)
612static inline int sci_rxd_in(struct uart_port *port)
613{
614 if (port->mapbase == 0xffe00000)
615 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
616 return 1;
617}
618#elif defined(__H8300H__) || defined(__H8300S__)
619static inline int sci_rxd_in(struct uart_port *port)
620{
621 int ch = (port->mapbase - SMR0) >> 3;
622 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
623}
624#else /* default case for non-SCI processors */
625static inline int sci_rxd_in(struct uart_port *port)
626{
627 return 1;
628}
629#endif
630
631/*
632 * Values for the BitRate Register (SCBRR)
633 *
634 * The values are actually divisors for a frequency which can
635 * be internal to the SH3 (14.7456MHz) or derived from an external
636 * clock source. This driver assumes the internal clock is used;
637 * to support using an external clock source, config options or
638 * possibly command-line options would need to be added.
639 *
640 * Also, to support speeds below 2400 (why?) the lower 2 bits of
641 * the SCSMR register would also need to be set to non-zero values.
642 *
643 * -- Greg Banks 27Feb2000
644 *
645 * Answer: The SCBRR register is only eight bits, and the value in
646 * it gets larger with lower baud rates. At around 2400 (depending on
647 * the peripherial module clock) you run out of bits. However the
648 * lower two bits of SCSMR allow the module clock to be divided down,
649 * scaling the value which is needed in SCBRR.
650 *
651 * -- Stuart Menefy - 23 May 2000
652 *
653 * I meant, why would anyone bother with bitrates below 2400.
654 *
655 * -- Greg Banks - 7Jul2000
656 *
657 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
658 * tape reader as a console!
659 *
660 * -- Mitch Davis - 15 Jul 2000
661 */
662
663#if (defined(CONFIG_CPU_SH7780) || \
664 defined(CONFIG_CPU_SH7785) || \
665 defined(CONFIG_CPU_SH7786)) && \
666 !defined(CONFIG_SH_SH2007)
667#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
668#elif defined(CONFIG_CPU_SH7705) || \
669 defined(CONFIG_CPU_SH7720) || \
670 defined(CONFIG_CPU_SH7721) || \
671 defined(CONFIG_ARCH_SH7367) || \
672 defined(CONFIG_ARCH_SH7377) || \
673 defined(CONFIG_ARCH_SH7372)
674#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
675#elif defined(CONFIG_CPU_SH7723) ||\
676 defined(CONFIG_CPU_SH7724)
677static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
678{
679 if (port->type == PORT_SCIF)
680 return (clk+16*bps)/(32*bps)-1;
681 else
682 return ((clk*2)+16*bps)/(16*bps)-1;
683}
684#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
685#elif defined(__H8300H__) || defined(__H8300S__)
686#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
687#else /* Generic SH */
688#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
689#endif