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git01.mediatek.com / filogic / uboot / a5464582e387428f9dbb1fcaf4626171554f2639 / . / board / google / chromebook_link / Kconfig
blob: 944716d002c9d0043d81cfa85af2ca9ec19b7c10 [file] [log] [blame]
Simon Glass446e56a2017-01-16 07:04:27 -0700[diff] [blame]1if TARGET_CHROMEBOOK_LINK || TARGET_CHROMEBOOK_LINK64
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]2
3config SYS_BOARD
4 default "chromebook_link"
5
6config SYS_VENDOR
7 default "google"
8
9config SYS_SOC
10 default "ivybridge"
11
12config SYS_CONFIG_NAME
13 default "chromebook_link"
14
Bin Mengd069c212015-04-27 23:22:28 +0800[diff] [blame]15config SYS_TEXT_BASE
Simon Glass5dd426f2017-01-16 07:04:22 -0700[diff] [blame]16 default 0xfff00000 if !SUPPORT_SPL
17 default 0x10000000 if SUPPORT_SPL
Bin Mengd069c212015-04-27 23:22:28 +0800[diff] [blame]18
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]19config BOARD_SPECIFIC_OPTIONS # dummy
20 def_bool y
Bin Menga11937c2015-01-06 22:14:15 +0800[diff] [blame]21 select X86_RESET_VECTOR
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]22 select NORTHBRIDGE_INTEL_IVYBRIDGE
Bin Mengc3153b32015-12-11 02:55:49 -0800[diff] [blame]23 select HAVE_INTEL_ME
Bin Mengc191ab72014-12-12 21:05:19 +0800[diff] [blame]24 select BOARD_ROMSIZE_KB_8192
Bin Meng19ca4632017-07-30 06:23:26 -0700[diff] [blame]25 select SPI_FLASH_WINBOND
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]26
Simon Glass461cebf2015-01-27 22:13:33 -0700[diff] [blame]27config PCIE_ECAM_BASE
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]28 default 0xf0000000
29
Simon Glass245561d2014-11-12 22:42:09 -0700[diff] [blame]30config EARLY_POST_CROS_EC
31 bool "Enable early post to Chrome OS EC"
32 default y
33
Bin Meng3705d1c2015-01-06 22:14:19 +0800[diff] [blame]34config SYS_CAR_ADDR
35 hex
36 default 0xff7e0000
37
38config SYS_CAR_SIZE
39 hex
40 default 0x20000
41
Simon Glass0b36ecd2014-11-12 22:42:07 -0700[diff] [blame]42endif