| Jit Loon Lim | 977071e | 2024-03-12 22:01:03 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2024 Intel Corporation. All rights reserved |
| 4 | */ |
| 5 | |
| 6 | #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H |
| 7 | #define _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H |
| 8 | |
| 9 | /* PER0MODRST */ |
| 10 | #define EMAC0_RESET 0 |
| 11 | #define EMAC1_RESET 1 |
| 12 | #define EMAC2_RESET 2 |
| 13 | #define USB0_RESET 3 |
| 14 | #define USB1_RESET 4 |
| 15 | #define NAND_RESET 5 |
| 16 | #define COMBOPHY_RESET 6 |
| 17 | #define SDMMC_RESET 7 |
| 18 | #define EMAC0_OCP_RESET 8 |
| 19 | #define EMAC1_OCP_RESET 9 |
| 20 | #define EMAC2_OCP_RESET 10 |
| 21 | #define USB0_OCP_RESET 11 |
| 22 | #define USB1_OCP_RESET 12 |
| 23 | #define NAND_OCP_RESET 13 |
| 24 | /* 14 is empty */ |
| 25 | #define SDMMC_OCP_RESET 15 |
| 26 | #define DMA_RESET 16 |
| 27 | #define SPIM0_RESET 17 |
| 28 | #define SPIM1_RESET 18 |
| 29 | #define SPIS0_RESET 19 |
| 30 | #define SPIS1_RESET 20 |
| 31 | #define DMA_OCP_RESET 21 |
| 32 | #define EMAC_PTP_RESET 22 |
| 33 | /* 23 is empty*/ |
| 34 | #define DMAIF0_RESET 24 |
| 35 | #define DMAIF1_RESET 25 |
| 36 | #define DMAIF2_RESET 26 |
| 37 | #define DMAIF3_RESET 27 |
| 38 | #define DMAIF4_RESET 28 |
| 39 | #define DMAIF5_RESET 29 |
| 40 | #define DMAIF6_RESET 30 |
| 41 | #define DMAIF7_RESET 31 |
| 42 | |
| 43 | /* PER1MODRST */ |
| 44 | #define WATCHDOG0_RESET 32 |
| 45 | #define WATCHDOG1_RESET 33 |
| 46 | #define WATCHDOG2_RESET 34 |
| 47 | #define WATCHDOG3_RESET 35 |
| 48 | #define L4SYSTIMER0_RESET 36 |
| 49 | #define L4SYSTIMER1_RESET 37 |
| 50 | #define SPTIMER0_RESET 38 |
| 51 | #define SPTIMER1_RESET 39 |
| 52 | #define I2C0_RESET 40 |
| 53 | #define I2C1_RESET 41 |
| 54 | #define I2C2_RESET 42 |
| 55 | #define I2C3_RESET 43 |
| 56 | #define I2C4_RESET 44 |
| 57 | #define I3C0_RESET 45 |
| 58 | #define I3C1_RESET 46 |
| 59 | /* 47 is empty */ |
| 60 | #define UART0_RESET 48 |
| 61 | #define UART1_RESET 49 |
| 62 | /* 50-55 is empty */ |
| 63 | #define GPIO0_RESET 56 |
| 64 | #define GPIO1_RESET 57 |
| 65 | #define WATCHDOG4_RESET 58 |
| 66 | /* 59-63 is empty */ |
| 67 | |
| 68 | /* BRGMODRST */ |
| 69 | #define SOC2FPGA_RESET 64 |
| 70 | #define LWHPS2FPGA_RESET 65 |
| 71 | #define FPGA2SOC_RESET 66 |
| 72 | #define F2SSDRAM_RESET 67 |
| 73 | /* 68-69 is empty */ |
| 74 | #define DDRSCH_RESET 70 |
| 75 | /* 71-95 is empty */ |
| 76 | |
| 77 | /* DBGMODRST */ |
| 78 | #define DBG_RESET 192 |
| 79 | |
| 80 | #endif |