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git01.mediatek.com / filogic / uboot / a52d20723b7f36fae0e0061c335328b6694b08c5 / . / dts / upstream / src / arm64 / ti / k3-am68-sk-base-board.dts
blob: d0cfdeac21fbe12b979e4b70062e58cf1f22d934 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
4 *
5 * Base Board: https://www.ti.com/lit/zip/SPRR463
6 */
7
8/dts-v1/;
9
10#include "k3-am68-sk-som.dtsi"
11#include <dt-bindings/net/ti-dp83867.h>
12#include <dt-bindings/phy/phy-cadence.h>
13#include <dt-bindings/phy/phy.h>
14
15#include "k3-serdes.h"
16
17/ {
18 compatible = "ti,am68-sk", "ti,j721s2";
19 model = "Texas Instruments AM68 SK";
20
21 chosen {
22 stdout-path = "serial2:115200n8";
23 };
24
25 aliases {
26 serial0 = &wkup_uart0;
27 serial1 = &mcu_uart0;
28 serial2 = &main_uart8;
29 mmc1 = &main_sdhci1;
30 can0 = &mcu_mcan0;
31 can1 = &mcu_mcan1;
32 can2 = &main_mcan6;
33 can3 = &main_mcan7;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]34 ethernet0 = &cpsw_port1;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]35 };
36
37 vusb_main: regulator-vusb-main5v0 {
38 /* USB MAIN INPUT 5V DC */
39 compatible = "regulator-fixed";
40 regulator-name = "vusb-main5v0";
41 regulator-min-microvolt = <5000000>;
42 regulator-max-microvolt = <5000000>;
43 regulator-always-on;
44 regulator-boot-on;
45 };
46
47 vsys_3v3: regulator-vsys3v3 {
48 /* Output of LM5141 */
49 compatible = "regulator-fixed";
50 regulator-name = "vsys_3v3";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 vin-supply = <&vusb_main>;
54 regulator-always-on;
55 regulator-boot-on;
56 };
57
58 vdd_mmc1: regulator-sd {
59 /* Output of TPS22918 */
60 compatible = "regulator-fixed";
61 regulator-name = "vdd_mmc1";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
64 regulator-boot-on;
65 enable-active-high;
66 vin-supply = <&vsys_3v3>;
67 gpio = <&exp1 8 GPIO_ACTIVE_HIGH>;
68 };
69
70 vdd_sd_dv: regulator-tlv71033 {
71 /* Output of TLV71033 */
72 compatible = "regulator-gpio";
73 regulator-name = "tlv71033";
74 pinctrl-names = "default";
75 pinctrl-0 = <&vdd_sd_dv_pins_default>;
76 regulator-min-microvolt = <1800000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-boot-on;
79 vin-supply = <&vsys_3v3>;
80 gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
81 states = <1800000 0x0>,
82 <3300000 0x1>;
83 };
84
85 vsys_io_1v8: regulator-vsys-io-1v8 {
86 compatible = "regulator-fixed";
87 regulator-name = "vsys_io_1v8";
88 regulator-min-microvolt = <1800000>;
89 regulator-max-microvolt = <1800000>;
90 regulator-always-on;
91 regulator-boot-on;
92 };
93
94 vsys_io_1v2: regulator-vsys-io-1v2 {
95 compatible = "regulator-fixed";
96 regulator-name = "vsys_io_1v2";
97 regulator-min-microvolt = <1200000>;
98 regulator-max-microvolt = <1200000>;
99 regulator-always-on;
100 regulator-boot-on;
101 };
102
103 transceiver1: can-phy0 {
104 compatible = "ti,tcan1042";
105 #phy-cells = <0>;
106 max-bitrate = <5000000>;
107 };
108
109 transceiver2: can-phy1 {
110 compatible = "ti,tcan1042";
111 #phy-cells = <0>;
112 max-bitrate = <5000000>;
113 };
114
115 transceiver3: can-phy2 {
116 compatible = "ti,tcan1042";
117 #phy-cells = <0>;
118 max-bitrate = <5000000>;
119 };
120
121 transceiver4: can-phy3 {
122 compatible = "ti,tcan1042";
123 #phy-cells = <0>;
124 max-bitrate = <5000000>;
125 };
126
127 connector-hdmi {
128 compatible = "hdmi-connector";
129 label = "hdmi";
130 type = "a";
131 pinctrl-names = "default";
132 pinctrl-0 = <&hdmi_hpd_pins_default>;
133 ddc-i2c-bus = <&mcu_i2c1>;
134 /* HDMI_HPD */
135 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
136
137 port {
138 hdmi_connector_in: endpoint {
139 remote-endpoint = <&tfp410_out>;
140 };
141 };
142 };
143
144 bridge-dvi {
145 compatible = "ti,tfp410";
146 /* HDMI_PDn */
147 powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>;
148 ti,deskew = <0>;
149
150 ports {
151 #address-cells = <1>;
152 #size-cells = <0>;
153
154 port@0 {
155 reg = <0>;
156
157 tfp410_in: endpoint {
158 remote-endpoint = <&dpi_out0>;
159 pclk-sample = <1>;
160 };
161 };
162
163 port@1 {
164 reg = <1>;
165
166 tfp410_out: endpoint {
167 remote-endpoint = <&hdmi_connector_in>;
168 };
169 };
170 };
171 };
172};
173
174&main_pmx0 {
175 main_uart8_pins_default: main-uart8-default-pins {
176 pinctrl-single,pins = <
177 J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
178 J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
179 >;
180 };
181
182 main_i2c0_pins_default: main-i2c0-default-pins {
183 pinctrl-single,pins = <
184 J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */
185 J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */
186 >;
187 };
188
189 main_mmc1_pins_default: main-mmc1-default-pins {
190 pinctrl-single,pins = <
191 J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
192 J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
193 J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
194 J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
195 J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
196 J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
197 J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
198 >;
199 };
200
201 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
202 pinctrl-single,pins = <
203 J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */
204 >;
205 };
206
207 main_usbss0_pins_default: main-usbss0-default-pins {
208 pinctrl-single,pins = <
209 J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
210 >;
211 };
212
213 main_mcan6_pins_default: main-mcan6-default-pins {
214 pinctrl-single,pins = <
215 J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */
216 J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */
217 >;
218 };
219
220 main_mcan7_pins_default: main-mcan7-default-pins {
221 pinctrl-single,pins = <
222 J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */
223 J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */
224 >;
225 };
226
227 main_i2c4_pins_default: main-i2c4-default-pins {
228 pinctrl-single,pins = <
229 J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */
230 J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */
231 >;
232 };
233
234 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
235 pinctrl-single,pins = <
236 J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */
237 J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */
238 J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */
239 J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */
240 J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */
241 J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */
242 J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */
243 J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */
244 J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */
245 J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */
246 J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */
247 J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */
248 J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */
249 J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */
250 >;
251 };
252
253 dss_vout0_pins_default: dss-vout0-default-pins {
254 pinctrl-single,pins = <
255 J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */
256 J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */
257 J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */
258 J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */
259 J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */
260 J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */
261 J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */
262 J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */
263 J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */
264 J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */
265 J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */
266 J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */
267 J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */
268 J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */
269 J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */
270 J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */
271 J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */
272 J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */
273 J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */
274 J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */
275 J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */
276 J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */
277 J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */
278 J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */
279 J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */
280 J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */
281 J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */
282 J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */
283 >;
284 };
285
286 hdmi_hpd_pins_default: hdmi-hpd-default-pins {
287 pinctrl-single,pins = <
288 J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */
289 >;
290 };
291};
292
293&wkup_pmx2 {
294 wkup_uart0_pins_default: wkup-uart0-default-pins {
295 pinctrl-single,pins = <
296 J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
297 J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
298 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
299 J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
300 >;
301 };
302
303 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
304 pinctrl-single,pins = <
305 J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
306 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
307 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
308 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
309 J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
310 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
311 J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
312 J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
313 J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
314 J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
315 J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
316 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
317 >;
318 };
319
320 mcu_mdio_pins_default: mcu-mdio-default-pins {
321 pinctrl-single,pins = <
322 J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
323 J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
324 >;
325 };
326
327 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
328 pinctrl-single,pins = <
329 J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
330 J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
331 >;
332 };
333
334 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
335 pinctrl-single,pins = <
336 J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
337 J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
338 >;
339 };
340
341 mcu_i2c0_pins_default: mcu-i2c0-default-pins {
342 pinctrl-single,pins = <
343 J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */
344 J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */
345 >;
346 };
347
348 mcu_i2c1_pins_default: mcu-i2c1-default-pins {
349 pinctrl-single,pins = <
350 J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
351 J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
352 >;
353 };
354
355 mcu_uart0_pins_default: mcu-uart0-default-pins {
356 pinctrl-single,pins = <
357 J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
358 J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
359 >;
360 };
361
362 mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 {
363 pinctrl-single,pins = <
364 J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
365 J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
366 J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
367 J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
368 J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
369 J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
370 J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
371 J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
372 J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
373 >;
374 };
375};
376
377&wkup_pmx3 {
378 mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 {
379 pinctrl-single,pins = <
380 J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
381 >;
382 };
383};
384
385&main_gpio0 {
386 status = "okay";
387 pinctrl-names = "default";
388 pinctrl-0 = <&rpi_header_gpio0_pins_default>;
389};
390
391&wkup_gpio0 {
392 status = "okay";
393 pinctrl-names = "default";
394 pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>;
395};
396
397&wkup_uart0 {
398 status = "reserved";
399 pinctrl-names = "default";
400 pinctrl-0 = <&wkup_uart0_pins_default>;
401};
402
403&mcu_uart0 {
404 status = "okay";
405 pinctrl-names = "default";
406 pinctrl-0 = <&mcu_uart0_pins_default>;
407};
408
409&main_uart8 {
410 status = "okay";
411 pinctrl-names = "default";
412 pinctrl-0 = <&main_uart8_pins_default>;
413 /* Shared with TFA on this platform */
414 power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
415};
416
417&main_i2c0 {
418 pinctrl-names = "default";
419 pinctrl-0 = <&main_i2c0_pins_default>;
420 clock-frequency = <400000>;
421
422 exp1: gpio@21 {
423 compatible = "ti,tca6416";
424 reg = <0x21>;
425 gpio-controller;
426 #gpio-cells = <2>;
427 gpio-line-names = " ", " ", " ", " ", " ",
428 "BOARDID_EEPROM_WP", "CAN_STB", " ",
429 "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz",
430 "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " ";
431 };
432};
433
434&main_i2c4 {
435 status = "okay";
436 pinctrl-names = "default";
437 pinctrl-0 = <&main_i2c4_pins_default>;
438 clock-frequency = <400000>;
439};
440
441&mcu_i2c0 {
442 status = "okay";
443 pinctrl-names = "default";
444 pinctrl-0 = <&mcu_i2c0_pins_default>;
445 clock-frequency = <400000>;
446};
447
448&mcu_i2c1 {
449 status = "okay";
450 pinctrl-names = "default";
451 pinctrl-0 = <&mcu_i2c1_pins_default>;
452 /* i2c1 is used for DVI DDC, so we need to use 100kHz */
453 clock-frequency = <100000>;
454
455 exp2: gpio@20 {
456 compatible = "ti,tca6408";
457 reg = <0x20>;
458 gpio-controller;
459 #gpio-cells = <2>;
460 gpio-line-names = "HDMI_PDn","HDMI_LS_OE",
461 "DP0_3V3_EN","eDP_ENABLE";
462 };
463};
464
465&main_sdhci1 {
466 /* SD card */
467 status = "okay";
468 pinctrl-0 = <&main_mmc1_pins_default>;
469 pinctrl-names = "default";
470 disable-wp;
471 vmmc-supply = <&vdd_mmc1>;
472 vqmmc-supply = <&vdd_sd_dv>;
473};
474
475&mcu_cpsw {
476 pinctrl-names = "default";
477 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
478};
479
480&davinci_mdio {
481 phy0: ethernet-phy@0 {
482 reg = <0>;
483 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
484 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
485 ti,min-output-impedance;
486 };
487};
488
489&cpsw_port1 {
490 phy-mode = "rgmii-rxid";
491 phy-handle = <&phy0>;
492};
493
494&mcu_mcan0 {
495 status = "okay";
496 pinctrl-names = "default";
497 pinctrl-0 = <&mcu_mcan0_pins_default>;
498 phys = <&transceiver1>;
499};
500
501&mcu_mcan1 {
502 status = "okay";
503 pinctrl-names = "default";
504 pinctrl-0 = <&mcu_mcan1_pins_default>;
505 phys = <&transceiver2>;
506};
507
508&main_mcan6 {
509 status = "okay";
510 pinctrl-names = "default";
511 pinctrl-0 = <&main_mcan6_pins_default>;
512 phys = <&transceiver3>;
513};
514
515&main_mcan7 {
516 status = "okay";
517 pinctrl-names = "default";
518 pinctrl-0 = <&main_mcan7_pins_default>;
519 phys = <&transceiver4>;
520};
521
522&dss {
523 status = "okay";
524 pinctrl-names = "default";
525 pinctrl-0 = <&dss_vout0_pins_default>;
526 /*
527 * These clock assignments are chosen to enable the following outputs:
528 *
529 * VP0 - DisplayPort SST
530 * VP1 - DPI0
531 * VP2 - DSI
532 * VP3 - DPI1
533 */
534 assigned-clocks = <&k3_clks 158 2>,
535 <&k3_clks 158 5>,
536 <&k3_clks 158 14>,
537 <&k3_clks 158 18>;
538 assigned-clock-parents = <&k3_clks 158 3>,
539 <&k3_clks 158 7>,
540 <&k3_clks 158 16>,
541 <&k3_clks 158 22>;
542};
543
544&dss_ports {
545 #address-cells = <1>;
546 #size-cells = <0>;
547
548 /* HDMI */
549 port@1 {
550 reg = <1>;
551
552 dpi_out0: endpoint {
553 remote-endpoint = <&tfp410_in>;
554 };
555 };
556};
557
558&serdes_ln_ctrl {
559 idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>,
560 <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>;
561};
562
563&serdes_refclk {
564 clock-frequency = <100000000>;
565};
566
567&serdes0 {
568 status = "okay";
569
570 serdes0_pcie_link: phy@0 {
571 reg = <0>;
572 cdns,num-lanes = <2>;
573 #phy-cells = <0>;
574 cdns,phy-type = <PHY_TYPE_PCIE>;
575 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
576 };
577
578 serdes0_usb_link: phy@2 {
579 status = "okay";
580 reg = <2>;
581 cdns,num-lanes = <1>;
582 #phy-cells = <0>;
583 cdns,phy-type = <PHY_TYPE_USB3>;
584 resets = <&serdes_wiz0 3>;
585 };
586};
587
588&pcie1_rc {
589 status = "okay";
590 reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>;
591 phys = <&serdes0_pcie_link>;
592 phy-names = "pcie-phy";
593 num-lanes = <2>;
594};
595
596&usb_serdes_mux {
597 idle-states = <0>; /* USB0 to SERDES lane 2 */
598};
599
600&usbss0 {
601 status = "okay";
602 pinctrl-0 = <&main_usbss0_pins_default>;
603 pinctrl-names = "default";
604 ti,vbus-divider;
605};
606
607&usb0 {
608 dr_mode = "host";
609 maximum-speed = "super-speed";
610 phys = <&serdes0_usb_link>;
611 phy-names = "cdns3,usb3-phy";
612};