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git01.mediatek.com / filogic / uboot / a52d20723b7f36fae0e0061c335328b6694b08c5 / . / dts / upstream / src / arm64 / qcom / sm8250.dtsi
blob: 760501c1301a6216fc22c48b388c4e69aa966a18 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8#include <dt-bindings/clock/qcom,gcc-sm8250.h>
9#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10#include <dt-bindings/clock/qcom,rpmh.h>
11#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
12#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
13#include <dt-bindings/dma/qcom-gpi.h>
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/interconnect/qcom,osm-l3.h>
16#include <dt-bindings/interconnect/qcom,sm8250.h>
17#include <dt-bindings/mailbox/qcom-ipcc.h>
18#include <dt-bindings/phy/phy-qcom-qmp.h>
19#include <dt-bindings/power/qcom-rpmpd.h>
20#include <dt-bindings/power/qcom,rpmhpd.h>
21#include <dt-bindings/soc/qcom,apr.h>
22#include <dt-bindings/soc/qcom,rpmh-rsc.h>
23#include <dt-bindings/sound/qcom,q6afe.h>
24#include <dt-bindings/thermal/thermal.h>
25#include <dt-bindings/clock/qcom,camcc-sm8250.h>
26#include <dt-bindings/clock/qcom,videocc-sm8250.h>
27
28/ {
29 interrupt-parent = <&intc>;
30
31 #address-cells = <2>;
32 #size-cells = <2>;
33
34 aliases {
35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 i2c3 = &i2c3;
39 i2c4 = &i2c4;
40 i2c5 = &i2c5;
41 i2c6 = &i2c6;
42 i2c7 = &i2c7;
43 i2c8 = &i2c8;
44 i2c9 = &i2c9;
45 i2c10 = &i2c10;
46 i2c11 = &i2c11;
47 i2c12 = &i2c12;
48 i2c13 = &i2c13;
49 i2c14 = &i2c14;
50 i2c15 = &i2c15;
51 i2c16 = &i2c16;
52 i2c17 = &i2c17;
53 i2c18 = &i2c18;
54 i2c19 = &i2c19;
55 spi0 = &spi0;
56 spi1 = &spi1;
57 spi2 = &spi2;
58 spi3 = &spi3;
59 spi4 = &spi4;
60 spi5 = &spi5;
61 spi6 = &spi6;
62 spi7 = &spi7;
63 spi8 = &spi8;
64 spi9 = &spi9;
65 spi10 = &spi10;
66 spi11 = &spi11;
67 spi12 = &spi12;
68 spi13 = &spi13;
69 spi14 = &spi14;
70 spi15 = &spi15;
71 spi16 = &spi16;
72 spi17 = &spi17;
73 spi18 = &spi18;
74 spi19 = &spi19;
75 };
76
77 chosen { };
78
79 clocks {
80 xo_board: xo-board {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <38400000>;
84 clock-output-names = "xo_board";
85 };
86
87 sleep_clk: sleep-clk {
88 compatible = "fixed-clock";
89 clock-frequency = <32768>;
90 #clock-cells = <0>;
91 };
92 };
93
94 cpus {
95 #address-cells = <2>;
96 #size-cells = <0>;
97
98 CPU0: cpu@0 {
99 device_type = "cpu";
100 compatible = "qcom,kryo485";
101 reg = <0x0 0x0>;
102 clocks = <&cpufreq_hw 0>;
103 enable-method = "psci";
104 capacity-dmips-mhz = <448>;
105 dynamic-power-coefficient = <105>;
106 next-level-cache = <&L2_0>;
107 power-domains = <&CPU_PD0>;
108 power-domain-names = "psci";
109 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = <&cpu0_opp_table>;
111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
112 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
113 #cooling-cells = <2>;
114 L2_0: l2-cache {
115 compatible = "cache";
116 cache-level = <2>;
117 cache-size = <0x20000>;
118 cache-unified;
119 next-level-cache = <&L3_0>;
120 L3_0: l3-cache {
121 compatible = "cache";
122 cache-level = <3>;
123 cache-size = <0x400000>;
124 cache-unified;
125 };
126 };
127 };
128
129 CPU1: cpu@100 {
130 device_type = "cpu";
131 compatible = "qcom,kryo485";
132 reg = <0x0 0x100>;
133 clocks = <&cpufreq_hw 0>;
134 enable-method = "psci";
135 capacity-dmips-mhz = <448>;
136 dynamic-power-coefficient = <105>;
137 next-level-cache = <&L2_100>;
138 power-domains = <&CPU_PD1>;
139 power-domain-names = "psci";
140 qcom,freq-domain = <&cpufreq_hw 0>;
141 operating-points-v2 = <&cpu0_opp_table>;
142 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
143 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
144 #cooling-cells = <2>;
145 L2_100: l2-cache {
146 compatible = "cache";
147 cache-level = <2>;
148 cache-size = <0x20000>;
149 cache-unified;
150 next-level-cache = <&L3_0>;
151 };
152 };
153
154 CPU2: cpu@200 {
155 device_type = "cpu";
156 compatible = "qcom,kryo485";
157 reg = <0x0 0x200>;
158 clocks = <&cpufreq_hw 0>;
159 enable-method = "psci";
160 capacity-dmips-mhz = <448>;
161 dynamic-power-coefficient = <105>;
162 next-level-cache = <&L2_200>;
163 power-domains = <&CPU_PD2>;
164 power-domain-names = "psci";
165 qcom,freq-domain = <&cpufreq_hw 0>;
166 operating-points-v2 = <&cpu0_opp_table>;
167 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
168 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
169 #cooling-cells = <2>;
170 L2_200: l2-cache {
171 compatible = "cache";
172 cache-level = <2>;
173 cache-size = <0x20000>;
174 cache-unified;
175 next-level-cache = <&L3_0>;
176 };
177 };
178
179 CPU3: cpu@300 {
180 device_type = "cpu";
181 compatible = "qcom,kryo485";
182 reg = <0x0 0x300>;
183 clocks = <&cpufreq_hw 0>;
184 enable-method = "psci";
185 capacity-dmips-mhz = <448>;
186 dynamic-power-coefficient = <105>;
187 next-level-cache = <&L2_300>;
188 power-domains = <&CPU_PD3>;
189 power-domain-names = "psci";
190 qcom,freq-domain = <&cpufreq_hw 0>;
191 operating-points-v2 = <&cpu0_opp_table>;
192 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
193 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
194 #cooling-cells = <2>;
195 L2_300: l2-cache {
196 compatible = "cache";
197 cache-level = <2>;
198 cache-size = <0x20000>;
199 cache-unified;
200 next-level-cache = <&L3_0>;
201 };
202 };
203
204 CPU4: cpu@400 {
205 device_type = "cpu";
206 compatible = "qcom,kryo485";
207 reg = <0x0 0x400>;
208 clocks = <&cpufreq_hw 1>;
209 enable-method = "psci";
210 capacity-dmips-mhz = <1024>;
211 dynamic-power-coefficient = <379>;
212 next-level-cache = <&L2_400>;
213 power-domains = <&CPU_PD4>;
214 power-domain-names = "psci";
215 qcom,freq-domain = <&cpufreq_hw 1>;
216 operating-points-v2 = <&cpu4_opp_table>;
217 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
218 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>;
220 L2_400: l2-cache {
221 compatible = "cache";
222 cache-level = <2>;
223 cache-size = <0x40000>;
224 cache-unified;
225 next-level-cache = <&L3_0>;
226 };
227 };
228
229 CPU5: cpu@500 {
230 device_type = "cpu";
231 compatible = "qcom,kryo485";
232 reg = <0x0 0x500>;
233 clocks = <&cpufreq_hw 1>;
234 enable-method = "psci";
235 capacity-dmips-mhz = <1024>;
236 dynamic-power-coefficient = <379>;
237 next-level-cache = <&L2_500>;
238 power-domains = <&CPU_PD5>;
239 power-domain-names = "psci";
240 qcom,freq-domain = <&cpufreq_hw 1>;
241 operating-points-v2 = <&cpu4_opp_table>;
242 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
243 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
244 #cooling-cells = <2>;
245 L2_500: l2-cache {
246 compatible = "cache";
247 cache-level = <2>;
248 cache-size = <0x40000>;
249 cache-unified;
250 next-level-cache = <&L3_0>;
251 };
252 };
253
254 CPU6: cpu@600 {
255 device_type = "cpu";
256 compatible = "qcom,kryo485";
257 reg = <0x0 0x600>;
258 clocks = <&cpufreq_hw 1>;
259 enable-method = "psci";
260 capacity-dmips-mhz = <1024>;
261 dynamic-power-coefficient = <379>;
262 next-level-cache = <&L2_600>;
263 power-domains = <&CPU_PD6>;
264 power-domain-names = "psci";
265 qcom,freq-domain = <&cpufreq_hw 1>;
266 operating-points-v2 = <&cpu4_opp_table>;
267 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
268 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
269 #cooling-cells = <2>;
270 L2_600: l2-cache {
271 compatible = "cache";
272 cache-level = <2>;
273 cache-size = <0x40000>;
274 cache-unified;
275 next-level-cache = <&L3_0>;
276 };
277 };
278
279 CPU7: cpu@700 {
280 device_type = "cpu";
281 compatible = "qcom,kryo485";
282 reg = <0x0 0x700>;
283 clocks = <&cpufreq_hw 2>;
284 enable-method = "psci";
285 capacity-dmips-mhz = <1024>;
286 dynamic-power-coefficient = <444>;
287 next-level-cache = <&L2_700>;
288 power-domains = <&CPU_PD7>;
289 power-domain-names = "psci";
290 qcom,freq-domain = <&cpufreq_hw 2>;
291 operating-points-v2 = <&cpu7_opp_table>;
292 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
293 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
294 #cooling-cells = <2>;
295 L2_700: l2-cache {
296 compatible = "cache";
297 cache-level = <2>;
298 cache-size = <0x80000>;
299 cache-unified;
300 next-level-cache = <&L3_0>;
301 };
302 };
303
304 cpu-map {
305 cluster0 {
306 core0 {
307 cpu = <&CPU0>;
308 };
309
310 core1 {
311 cpu = <&CPU1>;
312 };
313
314 core2 {
315 cpu = <&CPU2>;
316 };
317
318 core3 {
319 cpu = <&CPU3>;
320 };
321
322 core4 {
323 cpu = <&CPU4>;
324 };
325
326 core5 {
327 cpu = <&CPU5>;
328 };
329
330 core6 {
331 cpu = <&CPU6>;
332 };
333
334 core7 {
335 cpu = <&CPU7>;
336 };
337 };
338 };
339
340 idle-states {
341 entry-method = "psci";
342
343 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
344 compatible = "arm,idle-state";
345 idle-state-name = "silver-rail-power-collapse";
346 arm,psci-suspend-param = <0x40000004>;
347 entry-latency-us = <360>;
348 exit-latency-us = <531>;
349 min-residency-us = <3934>;
350 local-timer-stop;
351 };
352
353 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
354 compatible = "arm,idle-state";
355 idle-state-name = "gold-rail-power-collapse";
356 arm,psci-suspend-param = <0x40000004>;
357 entry-latency-us = <702>;
358 exit-latency-us = <1061>;
359 min-residency-us = <4488>;
360 local-timer-stop;
361 };
362 };
363
364 domain-idle-states {
365 CLUSTER_SLEEP_0: cluster-sleep-0 {
366 compatible = "domain-idle-state";
367 arm,psci-suspend-param = <0x4100c244>;
368 entry-latency-us = <3264>;
369 exit-latency-us = <6562>;
370 min-residency-us = <9987>;
371 };
372 };
373 };
374
375 qup_virt: interconnect-qup-virt {
376 compatible = "qcom,sm8250-qup-virt";
377 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_voter>;
379 };
380
381 cpu0_opp_table: opp-table-cpu0 {
382 compatible = "operating-points-v2";
383 opp-shared;
384
385 cpu0_opp1: opp-300000000 {
386 opp-hz = /bits/ 64 <300000000>;
387 opp-peak-kBps = <800000 9600000>;
388 };
389
390 cpu0_opp2: opp-403200000 {
391 opp-hz = /bits/ 64 <403200000>;
392 opp-peak-kBps = <800000 9600000>;
393 };
394
395 cpu0_opp3: opp-518400000 {
396 opp-hz = /bits/ 64 <518400000>;
397 opp-peak-kBps = <800000 16588800>;
398 };
399
400 cpu0_opp4: opp-614400000 {
401 opp-hz = /bits/ 64 <614400000>;
402 opp-peak-kBps = <800000 16588800>;
403 };
404
405 cpu0_opp5: opp-691200000 {
406 opp-hz = /bits/ 64 <691200000>;
407 opp-peak-kBps = <800000 19660800>;
408 };
409
410 cpu0_opp6: opp-787200000 {
411 opp-hz = /bits/ 64 <787200000>;
412 opp-peak-kBps = <1804000 19660800>;
413 };
414
415 cpu0_opp7: opp-883200000 {
416 opp-hz = /bits/ 64 <883200000>;
417 opp-peak-kBps = <1804000 23347200>;
418 };
419
420 cpu0_opp8: opp-979200000 {
421 opp-hz = /bits/ 64 <979200000>;
422 opp-peak-kBps = <1804000 26419200>;
423 };
424
425 cpu0_opp9: opp-1075200000 {
426 opp-hz = /bits/ 64 <1075200000>;
427 opp-peak-kBps = <1804000 29491200>;
428 };
429
430 cpu0_opp10: opp-1171200000 {
431 opp-hz = /bits/ 64 <1171200000>;
432 opp-peak-kBps = <1804000 32563200>;
433 };
434
435 cpu0_opp11: opp-1248000000 {
436 opp-hz = /bits/ 64 <1248000000>;
437 opp-peak-kBps = <1804000 36249600>;
438 };
439
440 cpu0_opp12: opp-1344000000 {
441 opp-hz = /bits/ 64 <1344000000>;
442 opp-peak-kBps = <2188000 36249600>;
443 };
444
445 cpu0_opp13: opp-1420800000 {
446 opp-hz = /bits/ 64 <1420800000>;
447 opp-peak-kBps = <2188000 39321600>;
448 };
449
450 cpu0_opp14: opp-1516800000 {
451 opp-hz = /bits/ 64 <1516800000>;
452 opp-peak-kBps = <3072000 42393600>;
453 };
454
455 cpu0_opp15: opp-1612800000 {
456 opp-hz = /bits/ 64 <1612800000>;
457 opp-peak-kBps = <3072000 42393600>;
458 };
459
460 cpu0_opp16: opp-1708800000 {
461 opp-hz = /bits/ 64 <1708800000>;
462 opp-peak-kBps = <4068000 42393600>;
463 };
464
465 cpu0_opp17: opp-1804800000 {
466 opp-hz = /bits/ 64 <1804800000>;
467 opp-peak-kBps = <4068000 42393600>;
468 };
469 };
470
471 cpu4_opp_table: opp-table-cpu4 {
472 compatible = "operating-points-v2";
473 opp-shared;
474
475 cpu4_opp1: opp-710400000 {
476 opp-hz = /bits/ 64 <710400000>;
477 opp-peak-kBps = <1804000 19660800>;
478 };
479
480 cpu4_opp2: opp-825600000 {
481 opp-hz = /bits/ 64 <825600000>;
482 opp-peak-kBps = <2188000 23347200>;
483 };
484
485 cpu4_opp3: opp-940800000 {
486 opp-hz = /bits/ 64 <940800000>;
487 opp-peak-kBps = <2188000 26419200>;
488 };
489
490 cpu4_opp4: opp-1056000000 {
491 opp-hz = /bits/ 64 <1056000000>;
492 opp-peak-kBps = <3072000 26419200>;
493 };
494
495 cpu4_opp5: opp-1171200000 {
496 opp-hz = /bits/ 64 <1171200000>;
497 opp-peak-kBps = <3072000 29491200>;
498 };
499
500 cpu4_opp6: opp-1286400000 {
501 opp-hz = /bits/ 64 <1286400000>;
502 opp-peak-kBps = <4068000 29491200>;
503 };
504
505 cpu4_opp7: opp-1382400000 {
506 opp-hz = /bits/ 64 <1382400000>;
507 opp-peak-kBps = <4068000 32563200>;
508 };
509
510 cpu4_opp8: opp-1478400000 {
511 opp-hz = /bits/ 64 <1478400000>;
512 opp-peak-kBps = <4068000 32563200>;
513 };
514
515 cpu4_opp9: opp-1574400000 {
516 opp-hz = /bits/ 64 <1574400000>;
517 opp-peak-kBps = <5412000 39321600>;
518 };
519
520 cpu4_opp10: opp-1670400000 {
521 opp-hz = /bits/ 64 <1670400000>;
522 opp-peak-kBps = <5412000 42393600>;
523 };
524
525 cpu4_opp11: opp-1766400000 {
526 opp-hz = /bits/ 64 <1766400000>;
527 opp-peak-kBps = <5412000 45465600>;
528 };
529
530 cpu4_opp12: opp-1862400000 {
531 opp-hz = /bits/ 64 <1862400000>;
532 opp-peak-kBps = <6220000 45465600>;
533 };
534
535 cpu4_opp13: opp-1958400000 {
536 opp-hz = /bits/ 64 <1958400000>;
537 opp-peak-kBps = <6220000 48537600>;
538 };
539
540 cpu4_opp14: opp-2054400000 {
541 opp-hz = /bits/ 64 <2054400000>;
542 opp-peak-kBps = <7216000 48537600>;
543 };
544
545 cpu4_opp15: opp-2150400000 {
546 opp-hz = /bits/ 64 <2150400000>;
547 opp-peak-kBps = <7216000 51609600>;
548 };
549
550 cpu4_opp16: opp-2246400000 {
551 opp-hz = /bits/ 64 <2246400000>;
552 opp-peak-kBps = <7216000 51609600>;
553 };
554
555 cpu4_opp17: opp-2342400000 {
556 opp-hz = /bits/ 64 <2342400000>;
557 opp-peak-kBps = <8368000 51609600>;
558 };
559
560 cpu4_opp18: opp-2419200000 {
561 opp-hz = /bits/ 64 <2419200000>;
562 opp-peak-kBps = <8368000 51609600>;
563 };
564 };
565
566 cpu7_opp_table: opp-table-cpu7 {
567 compatible = "operating-points-v2";
568 opp-shared;
569
570 cpu7_opp1: opp-844800000 {
571 opp-hz = /bits/ 64 <844800000>;
572 opp-peak-kBps = <2188000 19660800>;
573 };
574
575 cpu7_opp2: opp-960000000 {
576 opp-hz = /bits/ 64 <960000000>;
577 opp-peak-kBps = <2188000 26419200>;
578 };
579
580 cpu7_opp3: opp-1075200000 {
581 opp-hz = /bits/ 64 <1075200000>;
582 opp-peak-kBps = <3072000 26419200>;
583 };
584
585 cpu7_opp4: opp-1190400000 {
586 opp-hz = /bits/ 64 <1190400000>;
587 opp-peak-kBps = <3072000 29491200>;
588 };
589
590 cpu7_opp5: opp-1305600000 {
591 opp-hz = /bits/ 64 <1305600000>;
592 opp-peak-kBps = <4068000 32563200>;
593 };
594
595 cpu7_opp6: opp-1401600000 {
596 opp-hz = /bits/ 64 <1401600000>;
597 opp-peak-kBps = <4068000 32563200>;
598 };
599
600 cpu7_opp7: opp-1516800000 {
601 opp-hz = /bits/ 64 <1516800000>;
602 opp-peak-kBps = <4068000 36249600>;
603 };
604
605 cpu7_opp8: opp-1632000000 {
606 opp-hz = /bits/ 64 <1632000000>;
607 opp-peak-kBps = <5412000 39321600>;
608 };
609
610 cpu7_opp9: opp-1747200000 {
611 opp-hz = /bits/ 64 <1708800000>;
612 opp-peak-kBps = <5412000 42393600>;
613 };
614
615 cpu7_opp10: opp-1862400000 {
616 opp-hz = /bits/ 64 <1862400000>;
617 opp-peak-kBps = <6220000 45465600>;
618 };
619
620 cpu7_opp11: opp-1977600000 {
621 opp-hz = /bits/ 64 <1977600000>;
622 opp-peak-kBps = <6220000 48537600>;
623 };
624
625 cpu7_opp12: opp-2073600000 {
626 opp-hz = /bits/ 64 <2073600000>;
627 opp-peak-kBps = <7216000 48537600>;
628 };
629
630 cpu7_opp13: opp-2169600000 {
631 opp-hz = /bits/ 64 <2169600000>;
632 opp-peak-kBps = <7216000 51609600>;
633 };
634
635 cpu7_opp14: opp-2265600000 {
636 opp-hz = /bits/ 64 <2265600000>;
637 opp-peak-kBps = <7216000 51609600>;
638 };
639
640 cpu7_opp15: opp-2361600000 {
641 opp-hz = /bits/ 64 <2361600000>;
642 opp-peak-kBps = <8368000 51609600>;
643 };
644
645 cpu7_opp16: opp-2457600000 {
646 opp-hz = /bits/ 64 <2457600000>;
647 opp-peak-kBps = <8368000 51609600>;
648 };
649
650 cpu7_opp17: opp-2553600000 {
651 opp-hz = /bits/ 64 <2553600000>;
652 opp-peak-kBps = <8368000 51609600>;
653 };
654
655 cpu7_opp18: opp-2649600000 {
656 opp-hz = /bits/ 64 <2649600000>;
657 opp-peak-kBps = <8368000 51609600>;
658 };
659
660 cpu7_opp19: opp-2745600000 {
661 opp-hz = /bits/ 64 <2745600000>;
662 opp-peak-kBps = <8368000 51609600>;
663 };
664
665 cpu7_opp20: opp-2841600000 {
666 opp-hz = /bits/ 64 <2841600000>;
667 opp-peak-kBps = <8368000 51609600>;
668 };
669 };
670
671 firmware {
672 scm: scm {
673 compatible = "qcom,scm-sm8250", "qcom,scm";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]674 qcom,dload-mode = <&tcsr 0x13000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]675 #reset-cells = <1>;
676 };
677 };
678
679 memory@80000000 {
680 device_type = "memory";
681 /* We expect the bootloader to fill in the size */
682 reg = <0x0 0x80000000 0x0 0x0>;
683 };
684
685 pmu {
686 compatible = "arm,armv8-pmuv3";
687 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
688 };
689
690 psci {
691 compatible = "arm,psci-1.0";
692 method = "smc";
693
694 CPU_PD0: power-domain-cpu0 {
695 #power-domain-cells = <0>;
696 power-domains = <&CLUSTER_PD>;
697 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
698 };
699
700 CPU_PD1: power-domain-cpu1 {
701 #power-domain-cells = <0>;
702 power-domains = <&CLUSTER_PD>;
703 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
704 };
705
706 CPU_PD2: power-domain-cpu2 {
707 #power-domain-cells = <0>;
708 power-domains = <&CLUSTER_PD>;
709 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
710 };
711
712 CPU_PD3: power-domain-cpu3 {
713 #power-domain-cells = <0>;
714 power-domains = <&CLUSTER_PD>;
715 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
716 };
717
718 CPU_PD4: power-domain-cpu4 {
719 #power-domain-cells = <0>;
720 power-domains = <&CLUSTER_PD>;
721 domain-idle-states = <&BIG_CPU_SLEEP_0>;
722 };
723
724 CPU_PD5: power-domain-cpu5 {
725 #power-domain-cells = <0>;
726 power-domains = <&CLUSTER_PD>;
727 domain-idle-states = <&BIG_CPU_SLEEP_0>;
728 };
729
730 CPU_PD6: power-domain-cpu6 {
731 #power-domain-cells = <0>;
732 power-domains = <&CLUSTER_PD>;
733 domain-idle-states = <&BIG_CPU_SLEEP_0>;
734 };
735
736 CPU_PD7: power-domain-cpu7 {
737 #power-domain-cells = <0>;
738 power-domains = <&CLUSTER_PD>;
739 domain-idle-states = <&BIG_CPU_SLEEP_0>;
740 };
741
742 CLUSTER_PD: power-domain-cpu-cluster0 {
743 #power-domain-cells = <0>;
744 domain-idle-states = <&CLUSTER_SLEEP_0>;
745 };
746 };
747
748 qup_opp_table: opp-table-qup {
749 compatible = "operating-points-v2";
750
751 opp-50000000 {
752 opp-hz = /bits/ 64 <50000000>;
753 required-opps = <&rpmhpd_opp_min_svs>;
754 };
755
756 opp-75000000 {
757 opp-hz = /bits/ 64 <75000000>;
758 required-opps = <&rpmhpd_opp_low_svs>;
759 };
760
761 opp-120000000 {
762 opp-hz = /bits/ 64 <120000000>;
763 required-opps = <&rpmhpd_opp_svs>;
764 };
765 };
766
767 reserved-memory {
768 #address-cells = <2>;
769 #size-cells = <2>;
770 ranges;
771
772 hyp_mem: memory@80000000 {
773 reg = <0x0 0x80000000 0x0 0x600000>;
774 no-map;
775 };
776
777 xbl_aop_mem: memory@80700000 {
778 reg = <0x0 0x80700000 0x0 0x160000>;
779 no-map;
780 };
781
782 cmd_db: memory@80860000 {
783 compatible = "qcom,cmd-db";
784 reg = <0x0 0x80860000 0x0 0x20000>;
785 no-map;
786 };
787
788 smem_mem: memory@80900000 {
789 reg = <0x0 0x80900000 0x0 0x200000>;
790 no-map;
791 };
792
793 removed_mem: memory@80b00000 {
794 reg = <0x0 0x80b00000 0x0 0x5300000>;
795 no-map;
796 };
797
798 camera_mem: memory@86200000 {
799 reg = <0x0 0x86200000 0x0 0x500000>;
800 no-map;
801 };
802
803 wlan_mem: memory@86700000 {
804 reg = <0x0 0x86700000 0x0 0x100000>;
805 no-map;
806 };
807
808 ipa_fw_mem: memory@86800000 {
809 reg = <0x0 0x86800000 0x0 0x10000>;
810 no-map;
811 };
812
813 ipa_gsi_mem: memory@86810000 {
814 reg = <0x0 0x86810000 0x0 0xa000>;
815 no-map;
816 };
817
818 gpu_mem: memory@8681a000 {
819 reg = <0x0 0x8681a000 0x0 0x2000>;
820 no-map;
821 };
822
823 npu_mem: memory@86900000 {
824 reg = <0x0 0x86900000 0x0 0x500000>;
825 no-map;
826 };
827
828 video_mem: memory@86e00000 {
829 reg = <0x0 0x86e00000 0x0 0x500000>;
830 no-map;
831 };
832
833 cvp_mem: memory@87300000 {
834 reg = <0x0 0x87300000 0x0 0x500000>;
835 no-map;
836 };
837
838 cdsp_mem: memory@87800000 {
839 reg = <0x0 0x87800000 0x0 0x1400000>;
840 no-map;
841 };
842
843 slpi_mem: memory@88c00000 {
844 reg = <0x0 0x88c00000 0x0 0x1500000>;
845 no-map;
846 };
847
848 adsp_mem: memory@8a100000 {
849 reg = <0x0 0x8a100000 0x0 0x1d00000>;
850 no-map;
851 };
852
853 spss_mem: memory@8be00000 {
854 reg = <0x0 0x8be00000 0x0 0x100000>;
855 no-map;
856 };
857
858 cdsp_secure_heap: memory@8bf00000 {
859 reg = <0x0 0x8bf00000 0x0 0x4600000>;
860 no-map;
861 };
862 };
863
864 smem {
865 compatible = "qcom,smem";
866 memory-region = <&smem_mem>;
867 hwlocks = <&tcsr_mutex 3>;
868 };
869
870 smp2p-adsp {
871 compatible = "qcom,smp2p";
872 qcom,smem = <443>, <429>;
873 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
874 IPCC_MPROC_SIGNAL_SMP2P
875 IRQ_TYPE_EDGE_RISING>;
876 mboxes = <&ipcc IPCC_CLIENT_LPASS
877 IPCC_MPROC_SIGNAL_SMP2P>;
878
879 qcom,local-pid = <0>;
880 qcom,remote-pid = <2>;
881
882 smp2p_adsp_out: master-kernel {
883 qcom,entry-name = "master-kernel";
884 #qcom,smem-state-cells = <1>;
885 };
886
887 smp2p_adsp_in: slave-kernel {
888 qcom,entry-name = "slave-kernel";
889 interrupt-controller;
890 #interrupt-cells = <2>;
891 };
892 };
893
894 smp2p-cdsp {
895 compatible = "qcom,smp2p";
896 qcom,smem = <94>, <432>;
897 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
898 IPCC_MPROC_SIGNAL_SMP2P
899 IRQ_TYPE_EDGE_RISING>;
900 mboxes = <&ipcc IPCC_CLIENT_CDSP
901 IPCC_MPROC_SIGNAL_SMP2P>;
902
903 qcom,local-pid = <0>;
904 qcom,remote-pid = <5>;
905
906 smp2p_cdsp_out: master-kernel {
907 qcom,entry-name = "master-kernel";
908 #qcom,smem-state-cells = <1>;
909 };
910
911 smp2p_cdsp_in: slave-kernel {
912 qcom,entry-name = "slave-kernel";
913 interrupt-controller;
914 #interrupt-cells = <2>;
915 };
916 };
917
918 smp2p-slpi {
919 compatible = "qcom,smp2p";
920 qcom,smem = <481>, <430>;
921 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
922 IPCC_MPROC_SIGNAL_SMP2P
923 IRQ_TYPE_EDGE_RISING>;
924 mboxes = <&ipcc IPCC_CLIENT_SLPI
925 IPCC_MPROC_SIGNAL_SMP2P>;
926
927 qcom,local-pid = <0>;
928 qcom,remote-pid = <3>;
929
930 smp2p_slpi_out: master-kernel {
931 qcom,entry-name = "master-kernel";
932 #qcom,smem-state-cells = <1>;
933 };
934
935 smp2p_slpi_in: slave-kernel {
936 qcom,entry-name = "slave-kernel";
937 interrupt-controller;
938 #interrupt-cells = <2>;
939 };
940 };
941
942 soc: soc@0 {
943 #address-cells = <2>;
944 #size-cells = <2>;
945 ranges = <0 0 0 0 0x10 0>;
946 dma-ranges = <0 0 0 0 0x10 0>;
947 compatible = "simple-bus";
948
949 gcc: clock-controller@100000 {
950 compatible = "qcom,gcc-sm8250";
951 reg = <0x0 0x00100000 0x0 0x1f0000>;
952 #clock-cells = <1>;
953 #reset-cells = <1>;
954 #power-domain-cells = <1>;
955 clock-names = "bi_tcxo",
956 "bi_tcxo_ao",
957 "sleep_clk";
958 clocks = <&rpmhcc RPMH_CXO_CLK>,
959 <&rpmhcc RPMH_CXO_CLK_A>,
960 <&sleep_clk>;
961 };
962
963 ipcc: mailbox@408000 {
964 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
965 reg = <0 0x00408000 0 0x1000>;
966 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
967 interrupt-controller;
968 #interrupt-cells = <3>;
969 #mbox-cells = <2>;
970 };
971
972 qfprom: efuse@784000 {
973 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
974 reg = <0 0x00784000 0 0x8ff>;
975 #address-cells = <1>;
976 #size-cells = <1>;
977
978 gpu_speed_bin: gpu_speed_bin@19b {
979 reg = <0x19b 0x1>;
980 bits = <5 3>;
981 };
982 };
983
984 rng: rng@793000 {
985 compatible = "qcom,prng-ee";
986 reg = <0 0x00793000 0 0x1000>;
987 clocks = <&gcc GCC_PRNG_AHB_CLK>;
988 clock-names = "core";
989 };
990
991 gpi_dma2: dma-controller@800000 {
992 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
993 reg = <0 0x00800000 0 0x70000>;
994 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1004 dma-channels = <10>;
1005 dma-channel-mask = <0x3f>;
1006 iommus = <&apps_smmu 0x76 0x0>;
1007 #dma-cells = <3>;
1008 status = "disabled";
1009 };
1010
1011 qupv3_id_2: geniqup@8c0000 {
1012 compatible = "qcom,geni-se-qup";
1013 reg = <0x0 0x008c0000 0x0 0x6000>;
1014 clock-names = "m-ahb", "s-ahb";
1015 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1016 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1017 #address-cells = <2>;
1018 #size-cells = <2>;
1019 iommus = <&apps_smmu 0x63 0x0>;
1020 ranges;
1021 status = "disabled";
1022
1023 i2c14: i2c@880000 {
1024 compatible = "qcom,geni-i2c";
1025 reg = <0 0x00880000 0 0x4000>;
1026 clock-names = "se";
1027 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_i2c14_default>;
1030 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1031 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1032 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1033 dma-names = "tx", "rx";
1034 power-domains = <&rpmhpd SM8250_CX>;
1035 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1036 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1037 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1038 interconnect-names = "qup-core",
1039 "qup-config",
1040 "qup-memory";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 status = "disabled";
1044 };
1045
1046 spi14: spi@880000 {
1047 compatible = "qcom,geni-spi";
1048 reg = <0 0x00880000 0 0x4000>;
1049 clock-names = "se";
1050 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1051 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1052 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1053 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1054 dma-names = "tx", "rx";
1055 power-domains = <&rpmhpd RPMHPD_CX>;
1056 operating-points-v2 = <&qup_opp_table>;
1057 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1058 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1059 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1060 interconnect-names = "qup-core",
1061 "qup-config",
1062 "qup-memory";
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065 status = "disabled";
1066 };
1067
1068 i2c15: i2c@884000 {
1069 compatible = "qcom,geni-i2c";
1070 reg = <0 0x00884000 0 0x4000>;
1071 clock-names = "se";
1072 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1073 pinctrl-names = "default";
1074 pinctrl-0 = <&qup_i2c15_default>;
1075 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1076 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1077 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1078 dma-names = "tx", "rx";
1079 power-domains = <&rpmhpd SM8250_CX>;
1080 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1081 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1082 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1083 interconnect-names = "qup-core",
1084 "qup-config",
1085 "qup-memory";
1086 #address-cells = <1>;
1087 #size-cells = <0>;
1088 status = "disabled";
1089 };
1090
1091 spi15: spi@884000 {
1092 compatible = "qcom,geni-spi";
1093 reg = <0 0x00884000 0 0x4000>;
1094 clock-names = "se";
1095 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1096 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1097 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1098 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1099 dma-names = "tx", "rx";
1100 power-domains = <&rpmhpd RPMHPD_CX>;
1101 operating-points-v2 = <&qup_opp_table>;
1102 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1103 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1104 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1105 interconnect-names = "qup-core",
1106 "qup-config",
1107 "qup-memory";
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 status = "disabled";
1111 };
1112
1113 i2c16: i2c@888000 {
1114 compatible = "qcom,geni-i2c";
1115 reg = <0 0x00888000 0 0x4000>;
1116 clock-names = "se";
1117 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&qup_i2c16_default>;
1120 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1121 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1122 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1123 dma-names = "tx", "rx";
1124 power-domains = <&rpmhpd SM8250_CX>;
1125 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1126 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1127 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1128 interconnect-names = "qup-core",
1129 "qup-config",
1130 "qup-memory";
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133 status = "disabled";
1134 };
1135
1136 spi16: spi@888000 {
1137 compatible = "qcom,geni-spi";
1138 reg = <0 0x00888000 0 0x4000>;
1139 clock-names = "se";
1140 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1141 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1142 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1143 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1144 dma-names = "tx", "rx";
1145 power-domains = <&rpmhpd RPMHPD_CX>;
1146 operating-points-v2 = <&qup_opp_table>;
1147 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1148 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1149 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1150 interconnect-names = "qup-core",
1151 "qup-config",
1152 "qup-memory";
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1155 status = "disabled";
1156 };
1157
1158 i2c17: i2c@88c000 {
1159 compatible = "qcom,geni-i2c";
1160 reg = <0 0x0088c000 0 0x4000>;
1161 clock-names = "se";
1162 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&qup_i2c17_default>;
1165 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1166 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1167 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1168 dma-names = "tx", "rx";
1169 power-domains = <&rpmhpd SM8250_CX>;
1170 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1171 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1172 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1173 interconnect-names = "qup-core",
1174 "qup-config",
1175 "qup-memory";
1176 #address-cells = <1>;
1177 #size-cells = <0>;
1178 status = "disabled";
1179 };
1180
1181 spi17: spi@88c000 {
1182 compatible = "qcom,geni-spi";
1183 reg = <0 0x0088c000 0 0x4000>;
1184 clock-names = "se";
1185 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1186 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1187 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1188 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1189 dma-names = "tx", "rx";
1190 power-domains = <&rpmhpd RPMHPD_CX>;
1191 operating-points-v2 = <&qup_opp_table>;
1192 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1193 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1194 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1195 interconnect-names = "qup-core",
1196 "qup-config",
1197 "qup-memory";
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1200 status = "disabled";
1201 };
1202
1203 uart17: serial@88c000 {
1204 compatible = "qcom,geni-uart";
1205 reg = <0 0x0088c000 0 0x4000>;
1206 clock-names = "se";
1207 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1208 pinctrl-names = "default";
1209 pinctrl-0 = <&qup_uart17_default>;
1210 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1211 power-domains = <&rpmhpd RPMHPD_CX>;
1212 operating-points-v2 = <&qup_opp_table>;
1213 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1214 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1215 interconnect-names = "qup-core",
1216 "qup-config";
1217 status = "disabled";
1218 };
1219
1220 i2c18: i2c@890000 {
1221 compatible = "qcom,geni-i2c";
1222 reg = <0 0x00890000 0 0x4000>;
1223 clock-names = "se";
1224 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1225 pinctrl-names = "default";
1226 pinctrl-0 = <&qup_i2c18_default>;
1227 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1228 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1229 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1230 dma-names = "tx", "rx";
1231 power-domains = <&rpmhpd SM8250_CX>;
1232 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1233 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1234 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1235 interconnect-names = "qup-core",
1236 "qup-config",
1237 "qup-memory";
1238 #address-cells = <1>;
1239 #size-cells = <0>;
1240 status = "disabled";
1241 };
1242
1243 spi18: spi@890000 {
1244 compatible = "qcom,geni-spi";
1245 reg = <0 0x00890000 0 0x4000>;
1246 clock-names = "se";
1247 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1248 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1249 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1250 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1251 dma-names = "tx", "rx";
1252 power-domains = <&rpmhpd RPMHPD_CX>;
1253 operating-points-v2 = <&qup_opp_table>;
1254 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1255 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1256 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1257 interconnect-names = "qup-core",
1258 "qup-config",
1259 "qup-memory";
1260 #address-cells = <1>;
1261 #size-cells = <0>;
1262 status = "disabled";
1263 };
1264
1265 uart18: serial@890000 {
1266 compatible = "qcom,geni-uart";
1267 reg = <0 0x00890000 0 0x4000>;
1268 clock-names = "se";
1269 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1270 pinctrl-names = "default";
1271 pinctrl-0 = <&qup_uart18_default>;
1272 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1273 power-domains = <&rpmhpd RPMHPD_CX>;
1274 operating-points-v2 = <&qup_opp_table>;
1275 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1276 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1277 interconnect-names = "qup-core",
1278 "qup-config";
1279 status = "disabled";
1280 };
1281
1282 i2c19: i2c@894000 {
1283 compatible = "qcom,geni-i2c";
1284 reg = <0 0x00894000 0 0x4000>;
1285 clock-names = "se";
1286 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1287 pinctrl-names = "default";
1288 pinctrl-0 = <&qup_i2c19_default>;
1289 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1290 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1291 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1292 dma-names = "tx", "rx";
1293 power-domains = <&rpmhpd SM8250_CX>;
1294 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1295 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1296 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1297 interconnect-names = "qup-core",
1298 "qup-config",
1299 "qup-memory";
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1302 status = "disabled";
1303 };
1304
1305 spi19: spi@894000 {
1306 compatible = "qcom,geni-spi";
1307 reg = <0 0x00894000 0 0x4000>;
1308 clock-names = "se";
1309 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1310 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1311 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1312 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1313 dma-names = "tx", "rx";
1314 power-domains = <&rpmhpd RPMHPD_CX>;
1315 operating-points-v2 = <&qup_opp_table>;
1316 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1317 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1318 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1319 interconnect-names = "qup-core",
1320 "qup-config",
1321 "qup-memory";
1322 #address-cells = <1>;
1323 #size-cells = <0>;
1324 status = "disabled";
1325 };
1326 };
1327
1328 gpi_dma0: dma-controller@900000 {
1329 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1330 reg = <0 0x00900000 0 0x70000>;
1331 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1344 dma-channels = <15>;
1345 dma-channel-mask = <0x7ff>;
1346 iommus = <&apps_smmu 0x5b6 0x0>;
1347 #dma-cells = <3>;
1348 status = "disabled";
1349 };
1350
1351 qupv3_id_0: geniqup@9c0000 {
1352 compatible = "qcom,geni-se-qup";
1353 reg = <0x0 0x009c0000 0x0 0x6000>;
1354 clock-names = "m-ahb", "s-ahb";
1355 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1356 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1357 #address-cells = <2>;
1358 #size-cells = <2>;
1359 iommus = <&apps_smmu 0x5a3 0x0>;
1360 ranges;
1361 status = "disabled";
1362
1363 i2c0: i2c@980000 {
1364 compatible = "qcom,geni-i2c";
1365 reg = <0 0x00980000 0 0x4000>;
1366 clock-names = "se";
1367 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1368 pinctrl-names = "default";
1369 pinctrl-0 = <&qup_i2c0_default>;
1370 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1371 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1372 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1373 dma-names = "tx", "rx";
1374 power-domains = <&rpmhpd SM8250_CX>;
1375 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1376 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1377 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1378 interconnect-names = "qup-core",
1379 "qup-config",
1380 "qup-memory";
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1383 status = "disabled";
1384 };
1385
1386 spi0: spi@980000 {
1387 compatible = "qcom,geni-spi";
1388 reg = <0 0x00980000 0 0x4000>;
1389 clock-names = "se";
1390 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1391 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1392 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1393 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1394 dma-names = "tx", "rx";
1395 power-domains = <&rpmhpd RPMHPD_CX>;
1396 operating-points-v2 = <&qup_opp_table>;
1397 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1398 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1399 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1400 interconnect-names = "qup-core",
1401 "qup-config",
1402 "qup-memory";
1403 #address-cells = <1>;
1404 #size-cells = <0>;
1405 status = "disabled";
1406 };
1407
1408 i2c1: i2c@984000 {
1409 compatible = "qcom,geni-i2c";
1410 reg = <0 0x00984000 0 0x4000>;
1411 clock-names = "se";
1412 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1413 pinctrl-names = "default";
1414 pinctrl-0 = <&qup_i2c1_default>;
1415 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1416 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1417 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1418 dma-names = "tx", "rx";
1419 power-domains = <&rpmhpd SM8250_CX>;
1420 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1421 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1422 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1423 interconnect-names = "qup-core",
1424 "qup-config",
1425 "qup-memory";
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1428 status = "disabled";
1429 };
1430
1431 spi1: spi@984000 {
1432 compatible = "qcom,geni-spi";
1433 reg = <0 0x00984000 0 0x4000>;
1434 clock-names = "se";
1435 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1436 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1437 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1438 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1439 dma-names = "tx", "rx";
1440 power-domains = <&rpmhpd RPMHPD_CX>;
1441 operating-points-v2 = <&qup_opp_table>;
1442 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1443 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1444 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1445 interconnect-names = "qup-core",
1446 "qup-config",
1447 "qup-memory";
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1450 status = "disabled";
1451 };
1452
1453 i2c2: i2c@988000 {
1454 compatible = "qcom,geni-i2c";
1455 reg = <0 0x00988000 0 0x4000>;
1456 clock-names = "se";
1457 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1458 pinctrl-names = "default";
1459 pinctrl-0 = <&qup_i2c2_default>;
1460 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1461 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1462 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1463 dma-names = "tx", "rx";
1464 power-domains = <&rpmhpd SM8250_CX>;
1465 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1466 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1467 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1468 interconnect-names = "qup-core",
1469 "qup-config",
1470 "qup-memory";
1471 #address-cells = <1>;
1472 #size-cells = <0>;
1473 status = "disabled";
1474 };
1475
1476 spi2: spi@988000 {
1477 compatible = "qcom,geni-spi";
1478 reg = <0 0x00988000 0 0x4000>;
1479 clock-names = "se";
1480 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1481 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1482 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1483 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1484 dma-names = "tx", "rx";
1485 power-domains = <&rpmhpd RPMHPD_CX>;
1486 operating-points-v2 = <&qup_opp_table>;
1487 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1488 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1489 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1490 interconnect-names = "qup-core",
1491 "qup-config",
1492 "qup-memory";
1493 #address-cells = <1>;
1494 #size-cells = <0>;
1495 status = "disabled";
1496 };
1497
1498 uart2: serial@988000 {
1499 compatible = "qcom,geni-debug-uart";
1500 reg = <0 0x00988000 0 0x4000>;
1501 clock-names = "se";
1502 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1503 pinctrl-names = "default";
1504 pinctrl-0 = <&qup_uart2_default>;
1505 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1506 power-domains = <&rpmhpd RPMHPD_CX>;
1507 operating-points-v2 = <&qup_opp_table>;
1508 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1509 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1510 interconnect-names = "qup-core",
1511 "qup-config";
1512 status = "disabled";
1513 };
1514
1515 i2c3: i2c@98c000 {
1516 compatible = "qcom,geni-i2c";
1517 reg = <0 0x0098c000 0 0x4000>;
1518 clock-names = "se";
1519 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1520 pinctrl-names = "default";
1521 pinctrl-0 = <&qup_i2c3_default>;
1522 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1523 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1524 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1525 dma-names = "tx", "rx";
1526 power-domains = <&rpmhpd SM8250_CX>;
1527 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1528 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1529 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1530 interconnect-names = "qup-core",
1531 "qup-config",
1532 "qup-memory";
1533 #address-cells = <1>;
1534 #size-cells = <0>;
1535 status = "disabled";
1536 };
1537
1538 spi3: spi@98c000 {
1539 compatible = "qcom,geni-spi";
1540 reg = <0 0x0098c000 0 0x4000>;
1541 clock-names = "se";
1542 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1543 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1544 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1545 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1546 dma-names = "tx", "rx";
1547 power-domains = <&rpmhpd RPMHPD_CX>;
1548 operating-points-v2 = <&qup_opp_table>;
1549 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1550 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1551 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1552 interconnect-names = "qup-core",
1553 "qup-config",
1554 "qup-memory";
1555 #address-cells = <1>;
1556 #size-cells = <0>;
1557 status = "disabled";
1558 };
1559
1560 i2c4: i2c@990000 {
1561 compatible = "qcom,geni-i2c";
1562 reg = <0 0x00990000 0 0x4000>;
1563 clock-names = "se";
1564 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&qup_i2c4_default>;
1567 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1568 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1569 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1570 dma-names = "tx", "rx";
1571 power-domains = <&rpmhpd SM8250_CX>;
1572 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1573 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1574 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1575 interconnect-names = "qup-core",
1576 "qup-config",
1577 "qup-memory";
1578 #address-cells = <1>;
1579 #size-cells = <0>;
1580 status = "disabled";
1581 };
1582
1583 spi4: spi@990000 {
1584 compatible = "qcom,geni-spi";
1585 reg = <0 0x00990000 0 0x4000>;
1586 clock-names = "se";
1587 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1588 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1589 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1590 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1591 dma-names = "tx", "rx";
1592 power-domains = <&rpmhpd RPMHPD_CX>;
1593 operating-points-v2 = <&qup_opp_table>;
1594 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1595 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1596 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1597 interconnect-names = "qup-core",
1598 "qup-config",
1599 "qup-memory";
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1602 status = "disabled";
1603 };
1604
1605 i2c5: i2c@994000 {
1606 compatible = "qcom,geni-i2c";
1607 reg = <0 0x00994000 0 0x4000>;
1608 clock-names = "se";
1609 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1610 pinctrl-names = "default";
1611 pinctrl-0 = <&qup_i2c5_default>;
1612 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1613 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1614 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1615 dma-names = "tx", "rx";
1616 power-domains = <&rpmhpd SM8250_CX>;
1617 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1618 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1619 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1620 interconnect-names = "qup-core",
1621 "qup-config",
1622 "qup-memory";
1623 #address-cells = <1>;
1624 #size-cells = <0>;
1625 status = "disabled";
1626 };
1627
1628 spi5: spi@994000 {
1629 compatible = "qcom,geni-spi";
1630 reg = <0 0x00994000 0 0x4000>;
1631 clock-names = "se";
1632 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1633 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1634 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1635 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1636 dma-names = "tx", "rx";
1637 power-domains = <&rpmhpd RPMHPD_CX>;
1638 operating-points-v2 = <&qup_opp_table>;
1639 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1640 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1641 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1642 interconnect-names = "qup-core",
1643 "qup-config",
1644 "qup-memory";
1645 #address-cells = <1>;
1646 #size-cells = <0>;
1647 status = "disabled";
1648 };
1649
1650 i2c6: i2c@998000 {
1651 compatible = "qcom,geni-i2c";
1652 reg = <0 0x00998000 0 0x4000>;
1653 clock-names = "se";
1654 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1655 pinctrl-names = "default";
1656 pinctrl-0 = <&qup_i2c6_default>;
1657 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1658 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1659 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1660 dma-names = "tx", "rx";
1661 power-domains = <&rpmhpd SM8250_CX>;
1662 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1663 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1664 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1665 interconnect-names = "qup-core",
1666 "qup-config",
1667 "qup-memory";
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1670 status = "disabled";
1671 };
1672
1673 spi6: spi@998000 {
1674 compatible = "qcom,geni-spi";
1675 reg = <0 0x00998000 0 0x4000>;
1676 clock-names = "se";
1677 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1678 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1679 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1680 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1681 dma-names = "tx", "rx";
1682 power-domains = <&rpmhpd RPMHPD_CX>;
1683 operating-points-v2 = <&qup_opp_table>;
1684 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1685 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1686 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1687 interconnect-names = "qup-core",
1688 "qup-config",
1689 "qup-memory";
1690 #address-cells = <1>;
1691 #size-cells = <0>;
1692 status = "disabled";
1693 };
1694
1695 uart6: serial@998000 {
1696 compatible = "qcom,geni-uart";
1697 reg = <0 0x00998000 0 0x4000>;
1698 clock-names = "se";
1699 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1700 pinctrl-names = "default";
1701 pinctrl-0 = <&qup_uart6_default>;
1702 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1703 power-domains = <&rpmhpd RPMHPD_CX>;
1704 operating-points-v2 = <&qup_opp_table>;
1705 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1706 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1707 interconnect-names = "qup-core",
1708 "qup-config";
1709 status = "disabled";
1710 };
1711
1712 i2c7: i2c@99c000 {
1713 compatible = "qcom,geni-i2c";
1714 reg = <0 0x0099c000 0 0x4000>;
1715 clock-names = "se";
1716 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1717 pinctrl-names = "default";
1718 pinctrl-0 = <&qup_i2c7_default>;
1719 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1720 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1721 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1722 dma-names = "tx", "rx";
1723 power-domains = <&rpmhpd SM8250_CX>;
1724 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1725 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1726 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1727 interconnect-names = "qup-core",
1728 "qup-config",
1729 "qup-memory";
1730 #address-cells = <1>;
1731 #size-cells = <0>;
1732 status = "disabled";
1733 };
1734
1735 spi7: spi@99c000 {
1736 compatible = "qcom,geni-spi";
1737 reg = <0 0x0099c000 0 0x4000>;
1738 clock-names = "se";
1739 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1740 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1741 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1742 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1743 dma-names = "tx", "rx";
1744 power-domains = <&rpmhpd RPMHPD_CX>;
1745 operating-points-v2 = <&qup_opp_table>;
1746 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1747 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1748 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1749 interconnect-names = "qup-core",
1750 "qup-config",
1751 "qup-memory";
1752 #address-cells = <1>;
1753 #size-cells = <0>;
1754 status = "disabled";
1755 };
1756 };
1757
1758 gpi_dma1: dma-controller@a00000 {
1759 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1760 reg = <0 0x00a00000 0 0x70000>;
1761 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1769 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1770 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1771 dma-channels = <10>;
1772 dma-channel-mask = <0x3f>;
1773 iommus = <&apps_smmu 0x56 0x0>;
1774 #dma-cells = <3>;
1775 status = "disabled";
1776 };
1777
1778 qupv3_id_1: geniqup@ac0000 {
1779 compatible = "qcom,geni-se-qup";
1780 reg = <0x0 0x00ac0000 0x0 0x6000>;
1781 clock-names = "m-ahb", "s-ahb";
1782 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1783 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1784 #address-cells = <2>;
1785 #size-cells = <2>;
1786 iommus = <&apps_smmu 0x43 0x0>;
1787 ranges;
1788 status = "disabled";
1789
1790 i2c8: i2c@a80000 {
1791 compatible = "qcom,geni-i2c";
1792 reg = <0 0x00a80000 0 0x4000>;
1793 clock-names = "se";
1794 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1795 pinctrl-names = "default";
1796 pinctrl-0 = <&qup_i2c8_default>;
1797 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1798 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1799 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1800 dma-names = "tx", "rx";
1801 power-domains = <&rpmhpd SM8250_CX>;
1802 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1803 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1804 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1805 interconnect-names = "qup-core",
1806 "qup-config",
1807 "qup-memory";
1808 #address-cells = <1>;
1809 #size-cells = <0>;
1810 status = "disabled";
1811 };
1812
1813 spi8: spi@a80000 {
1814 compatible = "qcom,geni-spi";
1815 reg = <0 0x00a80000 0 0x4000>;
1816 clock-names = "se";
1817 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1818 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1819 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1820 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1821 dma-names = "tx", "rx";
1822 power-domains = <&rpmhpd RPMHPD_CX>;
1823 operating-points-v2 = <&qup_opp_table>;
1824 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1825 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1826 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1827 interconnect-names = "qup-core",
1828 "qup-config",
1829 "qup-memory";
1830 #address-cells = <1>;
1831 #size-cells = <0>;
1832 status = "disabled";
1833 };
1834
1835 i2c9: i2c@a84000 {
1836 compatible = "qcom,geni-i2c";
1837 reg = <0 0x00a84000 0 0x4000>;
1838 clock-names = "se";
1839 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1840 pinctrl-names = "default";
1841 pinctrl-0 = <&qup_i2c9_default>;
1842 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1843 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1844 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1845 dma-names = "tx", "rx";
1846 power-domains = <&rpmhpd SM8250_CX>;
1847 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1848 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1849 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1850 interconnect-names = "qup-core",
1851 "qup-config",
1852 "qup-memory";
1853 #address-cells = <1>;
1854 #size-cells = <0>;
1855 status = "disabled";
1856 };
1857
1858 spi9: spi@a84000 {
1859 compatible = "qcom,geni-spi";
1860 reg = <0 0x00a84000 0 0x4000>;
1861 clock-names = "se";
1862 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1863 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1864 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1865 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1866 dma-names = "tx", "rx";
1867 power-domains = <&rpmhpd RPMHPD_CX>;
1868 operating-points-v2 = <&qup_opp_table>;
1869 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1870 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1871 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1872 interconnect-names = "qup-core",
1873 "qup-config",
1874 "qup-memory";
1875 #address-cells = <1>;
1876 #size-cells = <0>;
1877 status = "disabled";
1878 };
1879
1880 i2c10: i2c@a88000 {
1881 compatible = "qcom,geni-i2c";
1882 reg = <0 0x00a88000 0 0x4000>;
1883 clock-names = "se";
1884 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1885 pinctrl-names = "default";
1886 pinctrl-0 = <&qup_i2c10_default>;
1887 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1888 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1889 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1890 dma-names = "tx", "rx";
1891 power-domains = <&rpmhpd SM8250_CX>;
1892 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1893 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1894 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1895 interconnect-names = "qup-core",
1896 "qup-config",
1897 "qup-memory";
1898 #address-cells = <1>;
1899 #size-cells = <0>;
1900 status = "disabled";
1901 };
1902
1903 spi10: spi@a88000 {
1904 compatible = "qcom,geni-spi";
1905 reg = <0 0x00a88000 0 0x4000>;
1906 clock-names = "se";
1907 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1908 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1909 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1910 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1911 dma-names = "tx", "rx";
1912 power-domains = <&rpmhpd RPMHPD_CX>;
1913 operating-points-v2 = <&qup_opp_table>;
1914 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1915 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1916 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1917 interconnect-names = "qup-core",
1918 "qup-config",
1919 "qup-memory";
1920 #address-cells = <1>;
1921 #size-cells = <0>;
1922 status = "disabled";
1923 };
1924
1925 i2c11: i2c@a8c000 {
1926 compatible = "qcom,geni-i2c";
1927 reg = <0 0x00a8c000 0 0x4000>;
1928 clock-names = "se";
1929 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1930 pinctrl-names = "default";
1931 pinctrl-0 = <&qup_i2c11_default>;
1932 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1933 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1934 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1935 dma-names = "tx", "rx";
1936 power-domains = <&rpmhpd SM8250_CX>;
1937 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1938 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1939 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1940 interconnect-names = "qup-core",
1941 "qup-config",
1942 "qup-memory";
1943 #address-cells = <1>;
1944 #size-cells = <0>;
1945 status = "disabled";
1946 };
1947
1948 spi11: spi@a8c000 {
1949 compatible = "qcom,geni-spi";
1950 reg = <0 0x00a8c000 0 0x4000>;
1951 clock-names = "se";
1952 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1953 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1954 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1955 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1956 dma-names = "tx", "rx";
1957 power-domains = <&rpmhpd RPMHPD_CX>;
1958 operating-points-v2 = <&qup_opp_table>;
1959 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1960 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1961 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1962 interconnect-names = "qup-core",
1963 "qup-config",
1964 "qup-memory";
1965 #address-cells = <1>;
1966 #size-cells = <0>;
1967 status = "disabled";
1968 };
1969
1970 i2c12: i2c@a90000 {
1971 compatible = "qcom,geni-i2c";
1972 reg = <0 0x00a90000 0 0x4000>;
1973 clock-names = "se";
1974 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1975 pinctrl-names = "default";
1976 pinctrl-0 = <&qup_i2c12_default>;
1977 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1978 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1979 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1980 dma-names = "tx", "rx";
1981 power-domains = <&rpmhpd SM8250_CX>;
1982 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1983 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1984 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1985 interconnect-names = "qup-core",
1986 "qup-config",
1987 "qup-memory";
1988 #address-cells = <1>;
1989 #size-cells = <0>;
1990 status = "disabled";
1991 };
1992
1993 spi12: spi@a90000 {
1994 compatible = "qcom,geni-spi";
1995 reg = <0 0x00a90000 0 0x4000>;
1996 clock-names = "se";
1997 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1998 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2000 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2001 dma-names = "tx", "rx";
2002 power-domains = <&rpmhpd RPMHPD_CX>;
2003 operating-points-v2 = <&qup_opp_table>;
2004 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2005 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2006 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2007 interconnect-names = "qup-core",
2008 "qup-config",
2009 "qup-memory";
2010 #address-cells = <1>;
2011 #size-cells = <0>;
2012 status = "disabled";
2013 };
2014
2015 uart12: serial@a90000 {
2016 compatible = "qcom,geni-debug-uart";
2017 reg = <0x0 0x00a90000 0x0 0x4000>;
2018 clock-names = "se";
2019 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2020 pinctrl-names = "default";
2021 pinctrl-0 = <&qup_uart12_default>;
2022 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2023 power-domains = <&rpmhpd RPMHPD_CX>;
2024 operating-points-v2 = <&qup_opp_table>;
2025 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2026 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
2027 interconnect-names = "qup-core",
2028 "qup-config";
2029 status = "disabled";
2030 };
2031
2032 i2c13: i2c@a94000 {
2033 compatible = "qcom,geni-i2c";
2034 reg = <0 0x00a94000 0 0x4000>;
2035 clock-names = "se";
2036 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2037 pinctrl-names = "default";
2038 pinctrl-0 = <&qup_i2c13_default>;
2039 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2040 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2041 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2042 dma-names = "tx", "rx";
2043 power-domains = <&rpmhpd SM8250_CX>;
2044 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2045 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2046 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2047 interconnect-names = "qup-core",
2048 "qup-config",
2049 "qup-memory";
2050 #address-cells = <1>;
2051 #size-cells = <0>;
2052 status = "disabled";
2053 };
2054
2055 spi13: spi@a94000 {
2056 compatible = "qcom,geni-spi";
2057 reg = <0 0x00a94000 0 0x4000>;
2058 clock-names = "se";
2059 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2060 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2061 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2062 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2063 dma-names = "tx", "rx";
2064 power-domains = <&rpmhpd RPMHPD_CX>;
2065 operating-points-v2 = <&qup_opp_table>;
2066 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2067 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2068 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2069 interconnect-names = "qup-core",
2070 "qup-config",
2071 "qup-memory";
2072 #address-cells = <1>;
2073 #size-cells = <0>;
2074 status = "disabled";
2075 };
2076 };
2077
2078 config_noc: interconnect@1500000 {
2079 compatible = "qcom,sm8250-config-noc";
2080 reg = <0 0x01500000 0 0xa580>;
2081 #interconnect-cells = <2>;
2082 qcom,bcm-voters = <&apps_bcm_voter>;
2083 };
2084
2085 system_noc: interconnect@1620000 {
2086 compatible = "qcom,sm8250-system-noc";
2087 reg = <0 0x01620000 0 0x1c200>;
2088 #interconnect-cells = <2>;
2089 qcom,bcm-voters = <&apps_bcm_voter>;
2090 };
2091
2092 mc_virt: interconnect@163d000 {
2093 compatible = "qcom,sm8250-mc-virt";
2094 reg = <0 0x0163d000 0 0x1000>;
2095 #interconnect-cells = <2>;
2096 qcom,bcm-voters = <&apps_bcm_voter>;
2097 };
2098
2099 aggre1_noc: interconnect@16e0000 {
2100 compatible = "qcom,sm8250-aggre1-noc";
2101 reg = <0 0x016e0000 0 0x1f180>;
2102 #interconnect-cells = <2>;
2103 qcom,bcm-voters = <&apps_bcm_voter>;
2104 };
2105
2106 aggre2_noc: interconnect@1700000 {
2107 compatible = "qcom,sm8250-aggre2-noc";
2108 reg = <0 0x01700000 0 0x33000>;
2109 #interconnect-cells = <2>;
2110 qcom,bcm-voters = <&apps_bcm_voter>;
2111 };
2112
2113 compute_noc: interconnect@1733000 {
2114 compatible = "qcom,sm8250-compute-noc";
2115 reg = <0 0x01733000 0 0xa180>;
2116 #interconnect-cells = <2>;
2117 qcom,bcm-voters = <&apps_bcm_voter>;
2118 };
2119
2120 mmss_noc: interconnect@1740000 {
2121 compatible = "qcom,sm8250-mmss-noc";
2122 reg = <0 0x01740000 0 0x1f080>;
2123 #interconnect-cells = <2>;
2124 qcom,bcm-voters = <&apps_bcm_voter>;
2125 };
2126
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2127 pcie0: pcie@1c00000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2128 compatible = "qcom,pcie-sm8250";
2129 reg = <0 0x01c00000 0 0x3000>,
2130 <0 0x60000000 0 0xf1d>,
2131 <0 0x60000f20 0 0xa8>,
2132 <0 0x60001000 0 0x1000>,
2133 <0 0x60100000 0 0x100000>,
2134 <0 0x01c03000 0 0x1000>;
2135 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2136 device_type = "pci";
2137 linux,pci-domain = <0>;
2138 bus-range = <0x00 0xff>;
2139 num-lanes = <1>;
2140
2141 #address-cells = <3>;
2142 #size-cells = <2>;
2143
2144 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2145 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2146
2147 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2153 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2154 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2155 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2156 "msi4", "msi5", "msi6", "msi7";
2157 #interrupt-cells = <1>;
2158 interrupt-map-mask = <0 0 0 0x7>;
2159 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2160 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2161 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2162 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2163
2164 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2165 <&gcc GCC_PCIE_0_AUX_CLK>,
2166 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2167 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2168 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2169 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2170 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2171 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2172 clock-names = "pipe",
2173 "aux",
2174 "cfg",
2175 "bus_master",
2176 "bus_slave",
2177 "slave_q2a",
2178 "tbu",
2179 "ddrss_sf_tbu";
2180
2181 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2182 <0x100 &apps_smmu 0x1c01 0x1>;
2183
2184 resets = <&gcc GCC_PCIE_0_BCR>;
2185 reset-names = "pci";
2186
2187 power-domains = <&gcc PCIE_0_GDSC>;
2188
2189 phys = <&pcie0_phy>;
2190 phy-names = "pciephy";
2191
2192 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2193 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2194
2195 pinctrl-names = "default";
2196 pinctrl-0 = <&pcie0_default_state>;
2197 dma-coherent;
2198
2199 status = "disabled";
2200 };
2201
2202 pcie0_phy: phy@1c06000 {
2203 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2204 reg = <0 0x01c06000 0 0x1000>;
2205
2206 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2207 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2208 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2209 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
2210 <&gcc GCC_PCIE_0_PIPE_CLK>;
2211 clock-names = "aux",
2212 "cfg_ahb",
2213 "ref",
2214 "refgen",
2215 "pipe";
2216
2217 clock-output-names = "pcie_0_pipe_clk";
2218 #clock-cells = <0>;
2219
2220 #phy-cells = <0>;
2221
2222 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2223 reset-names = "phy";
2224
2225 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2226 assigned-clock-rates = <100000000>;
2227
2228 status = "disabled";
2229 };
2230
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2231 pcie1: pcie@1c08000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2232 compatible = "qcom,pcie-sm8250";
2233 reg = <0 0x01c08000 0 0x3000>,
2234 <0 0x40000000 0 0xf1d>,
2235 <0 0x40000f20 0 0xa8>,
2236 <0 0x40001000 0 0x1000>,
2237 <0 0x40100000 0 0x100000>,
2238 <0 0x01c0b000 0 0x1000>;
2239 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2240 device_type = "pci";
2241 linux,pci-domain = <1>;
2242 bus-range = <0x00 0xff>;
2243 num-lanes = <2>;
2244
2245 #address-cells = <3>;
2246 #size-cells = <2>;
2247
2248 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2249 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2250
2251 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2252 interrupt-names = "msi";
2253 #interrupt-cells = <1>;
2254 interrupt-map-mask = <0 0 0 0x7>;
2255 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2256 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2257 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2258 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2259
2260 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2261 <&gcc GCC_PCIE_1_AUX_CLK>,
2262 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2263 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2264 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2265 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2266 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2267 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2268 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2269 clock-names = "pipe",
2270 "aux",
2271 "cfg",
2272 "bus_master",
2273 "bus_slave",
2274 "slave_q2a",
2275 "ref",
2276 "tbu",
2277 "ddrss_sf_tbu";
2278
2279 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2280 assigned-clock-rates = <19200000>;
2281
2282 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2283 <0x100 &apps_smmu 0x1c81 0x1>;
2284
2285 resets = <&gcc GCC_PCIE_1_BCR>;
2286 reset-names = "pci";
2287
2288 power-domains = <&gcc PCIE_1_GDSC>;
2289
2290 phys = <&pcie1_phy>;
2291 phy-names = "pciephy";
2292
2293 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2294 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2295
2296 pinctrl-names = "default";
2297 pinctrl-0 = <&pcie1_default_state>;
2298 dma-coherent;
2299
2300 status = "disabled";
2301 };
2302
2303 pcie1_phy: phy@1c0e000 {
2304 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2305 reg = <0 0x01c0e000 0 0x1000>;
2306
2307 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2308 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2309 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2310 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2311 <&gcc GCC_PCIE_1_PIPE_CLK>;
2312 clock-names = "aux",
2313 "cfg_ahb",
2314 "ref",
2315 "refgen",
2316 "pipe";
2317
2318 clock-output-names = "pcie_1_pipe_clk";
2319 #clock-cells = <0>;
2320
2321 #phy-cells = <0>;
2322
2323 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2324 reset-names = "phy";
2325
2326 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2327 assigned-clock-rates = <100000000>;
2328
2329 status = "disabled";
2330 };
2331
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2332 pcie2: pcie@1c10000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2333 compatible = "qcom,pcie-sm8250";
2334 reg = <0 0x01c10000 0 0x3000>,
2335 <0 0x64000000 0 0xf1d>,
2336 <0 0x64000f20 0 0xa8>,
2337 <0 0x64001000 0 0x1000>,
2338 <0 0x64100000 0 0x100000>,
2339 <0 0x01c13000 0 0x1000>;
2340 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2341 device_type = "pci";
2342 linux,pci-domain = <2>;
2343 bus-range = <0x00 0xff>;
2344 num-lanes = <2>;
2345
2346 #address-cells = <3>;
2347 #size-cells = <2>;
2348
2349 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2350 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2351
2352 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2353 interrupt-names = "msi";
2354 #interrupt-cells = <1>;
2355 interrupt-map-mask = <0 0 0 0x7>;
2356 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2357 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2358 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2359 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2360
2361 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2362 <&gcc GCC_PCIE_2_AUX_CLK>,
2363 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2364 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2365 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2366 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2367 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2368 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2369 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2370 clock-names = "pipe",
2371 "aux",
2372 "cfg",
2373 "bus_master",
2374 "bus_slave",
2375 "slave_q2a",
2376 "ref",
2377 "tbu",
2378 "ddrss_sf_tbu";
2379
2380 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2381 assigned-clock-rates = <19200000>;
2382
2383 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2384 <0x100 &apps_smmu 0x1d01 0x1>;
2385
2386 resets = <&gcc GCC_PCIE_2_BCR>;
2387 reset-names = "pci";
2388
2389 power-domains = <&gcc PCIE_2_GDSC>;
2390
2391 phys = <&pcie2_phy>;
2392 phy-names = "pciephy";
2393
2394 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2395 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2396
2397 pinctrl-names = "default";
2398 pinctrl-0 = <&pcie2_default_state>;
2399 dma-coherent;
2400
2401 status = "disabled";
2402 };
2403
2404 pcie2_phy: phy@1c16000 {
2405 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2406 reg = <0 0x01c16000 0 0x1000>;
2407
2408 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2409 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2410 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2411 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
2412 <&gcc GCC_PCIE_2_PIPE_CLK>;
2413 clock-names = "aux",
2414 "cfg_ahb",
2415 "ref",
2416 "refgen",
2417 "pipe";
2418
2419 clock-output-names = "pcie_2_pipe_clk";
2420 #clock-cells = <0>;
2421
2422 #phy-cells = <0>;
2423
2424 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2425 reset-names = "phy";
2426
2427 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2428 assigned-clock-rates = <100000000>;
2429
2430 status = "disabled";
2431 };
2432
2433 ufs_mem_hc: ufshc@1d84000 {
2434 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2435 "jedec,ufs-2.0";
2436 reg = <0 0x01d84000 0 0x3000>;
2437 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2438 phys = <&ufs_mem_phy>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2439 phy-names = "ufsphy";
2440 lanes-per-direction = <2>;
2441 #reset-cells = <1>;
2442 resets = <&gcc GCC_UFS_PHY_BCR>;
2443 reset-names = "rst";
2444
2445 power-domains = <&gcc UFS_PHY_GDSC>;
2446
2447 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2448
2449 clock-names =
2450 "core_clk",
2451 "bus_aggr_clk",
2452 "iface_clk",
2453 "core_clk_unipro",
2454 "ref_clk",
2455 "tx_lane0_sync_clk",
2456 "rx_lane0_sync_clk",
2457 "rx_lane1_sync_clk";
2458 clocks =
2459 <&gcc GCC_UFS_PHY_AXI_CLK>,
2460 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2461 <&gcc GCC_UFS_PHY_AHB_CLK>,
2462 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2463 <&rpmhcc RPMH_CXO_CLK>,
2464 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2465 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2466 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2467
2468 operating-points-v2 = <&ufs_opp_table>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2469
2470 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2471 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2472 interconnect-names = "ufs-ddr", "cpu-ufs";
2473
2474 status = "disabled";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2475
2476 ufs_opp_table: opp-table {
2477 compatible = "operating-points-v2";
2478
2479 opp-37500000 {
2480 opp-hz = /bits/ 64 <37500000>,
2481 /bits/ 64 <0>,
2482 /bits/ 64 <0>,
2483 /bits/ 64 <37500000>,
2484 /bits/ 64 <0>,
2485 /bits/ 64 <0>,
2486 /bits/ 64 <0>,
2487 /bits/ 64 <0>;
2488 required-opps = <&rpmhpd_opp_low_svs>;
2489 };
2490
2491 opp-300000000 {
2492 opp-hz = /bits/ 64 <300000000>,
2493 /bits/ 64 <0>,
2494 /bits/ 64 <0>,
2495 /bits/ 64 <300000000>,
2496 /bits/ 64 <0>,
2497 /bits/ 64 <0>,
2498 /bits/ 64 <0>,
2499 /bits/ 64 <0>;
2500 required-opps = <&rpmhpd_opp_nom>;
2501 };
2502 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2503 };
2504
2505 ufs_mem_phy: phy@1d87000 {
2506 compatible = "qcom,sm8250-qmp-ufs-phy";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2507 reg = <0 0x01d87000 0 0x1000>;
2508
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2509 clock-names = "ref",
2510 "ref_aux";
2511 clocks = <&rpmhcc RPMH_CXO_CLK>,
2512 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2513
2514 resets = <&ufs_mem_hc 0>;
2515 reset-names = "ufsphy";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2516
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2517 #phy-cells = <0>;
2518
2519 status = "disabled";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2520 };
2521
2522 cryptobam: dma-controller@1dc4000 {
2523 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2524 reg = <0 0x01dc4000 0 0x24000>;
2525 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2526 #dma-cells = <1>;
2527 qcom,ee = <0>;
2528 qcom,controlled-remotely;
2529 num-channels = <8>;
2530 qcom,num-ees = <2>;
2531 iommus = <&apps_smmu 0x592 0x0000>,
2532 <&apps_smmu 0x598 0x0000>,
2533 <&apps_smmu 0x599 0x0000>,
2534 <&apps_smmu 0x59f 0x0000>,
2535 <&apps_smmu 0x586 0x0011>,
2536 <&apps_smmu 0x596 0x0011>;
2537 };
2538
2539 crypto: crypto@1dfa000 {
2540 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2541 reg = <0 0x01dfa000 0 0x6000>;
2542 dmas = <&cryptobam 4>, <&cryptobam 5>;
2543 dma-names = "rx", "tx";
2544 iommus = <&apps_smmu 0x592 0x0000>,
2545 <&apps_smmu 0x598 0x0000>,
2546 <&apps_smmu 0x599 0x0000>,
2547 <&apps_smmu 0x59f 0x0000>,
2548 <&apps_smmu 0x586 0x0011>,
2549 <&apps_smmu 0x596 0x0011>;
2550 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2551 interconnect-names = "memory";
2552 };
2553
2554 tcsr_mutex: hwlock@1f40000 {
2555 compatible = "qcom,tcsr-mutex";
2556 reg = <0x0 0x01f40000 0x0 0x40000>;
2557 #hwlock-cells = <1>;
2558 };
2559
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2560 tcsr: syscon@1fc0000 {
2561 compatible = "qcom,sm8250-tcsr", "syscon";
2562 reg = <0x0 0x1fc0000 0x0 0x30000>;
2563 };
2564
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2565 wsamacro: codec@3240000 {
2566 compatible = "qcom,sm8250-lpass-wsa-macro";
2567 reg = <0 0x03240000 0 0x1000>;
2568 clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2569 <&audiocc LPASS_CDC_WSA_NPL>,
2570 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2571 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2572 <&aoncc LPASS_CDC_VA_MCLK>,
2573 <&vamacro>;
2574
2575 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2576
2577 #clock-cells = <0>;
2578 clock-output-names = "mclk";
2579 #sound-dai-cells = <1>;
2580
2581 pinctrl-names = "default";
2582 pinctrl-0 = <&wsa_swr_active>;
2583
2584 status = "disabled";
2585 };
2586
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2587 swr0: soundwire@3250000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2588 reg = <0 0x03250000 0 0x2000>;
2589 compatible = "qcom,soundwire-v1.5.1";
2590 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2591 clocks = <&wsamacro>;
2592 clock-names = "iface";
2593
2594 qcom,din-ports = <2>;
2595 qcom,dout-ports = <6>;
2596
2597 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2598 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2599 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2600 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2601
2602 #sound-dai-cells = <1>;
2603 #address-cells = <2>;
2604 #size-cells = <0>;
2605
2606 status = "disabled";
2607 };
2608
2609 audiocc: clock-controller@3300000 {
2610 compatible = "qcom,sm8250-lpass-audiocc";
2611 reg = <0 0x03300000 0 0x30000>;
2612 #clock-cells = <1>;
2613 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2614 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2615 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2616 clock-names = "core", "audio", "bus";
2617 };
2618
2619 vamacro: codec@3370000 {
2620 compatible = "qcom,sm8250-lpass-va-macro";
2621 reg = <0 0x03370000 0 0x1000>;
2622 clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2623 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2624 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2625
2626 clock-names = "mclk", "macro", "dcodec";
2627
2628 #clock-cells = <0>;
2629 clock-output-names = "fsgen";
2630 #sound-dai-cells = <1>;
2631 };
2632
2633 rxmacro: rxmacro@3200000 {
2634 pinctrl-names = "default";
2635 pinctrl-0 = <&rx_swr_active>;
2636 compatible = "qcom,sm8250-lpass-rx-macro";
2637 reg = <0 0x03200000 0 0x1000>;
2638 status = "disabled";
2639
2640 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2641 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2642 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2643 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2644 <&vamacro>;
2645
2646 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2647
2648 #clock-cells = <0>;
2649 clock-output-names = "mclk";
2650 #sound-dai-cells = <1>;
2651 };
2652
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2653 swr1: soundwire@3210000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2654 reg = <0 0x03210000 0 0x2000>;
2655 compatible = "qcom,soundwire-v1.5.1";
2656 status = "disabled";
2657 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2658 clocks = <&rxmacro>;
2659 clock-names = "iface";
2660 label = "RX";
2661 qcom,din-ports = <0>;
2662 qcom,dout-ports = <5>;
2663
2664 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2665 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2666 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2667 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2668 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2669 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2670 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2671 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2672 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2673
2674 #sound-dai-cells = <1>;
2675 #address-cells = <2>;
2676 #size-cells = <0>;
2677 };
2678
2679 txmacro: txmacro@3220000 {
2680 pinctrl-names = "default";
2681 pinctrl-0 = <&tx_swr_active>;
2682 compatible = "qcom,sm8250-lpass-tx-macro";
2683 reg = <0 0x03220000 0 0x1000>;
2684 status = "disabled";
2685
2686 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2687 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2688 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2689 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2690 <&vamacro>;
2691
2692 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2693
2694 #clock-cells = <0>;
2695 clock-output-names = "mclk";
2696 #sound-dai-cells = <1>;
2697 };
2698
2699 /* tx macro */
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]2700 swr2: soundwire@3230000 {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]2701 reg = <0 0x03230000 0 0x2000>;
2702 compatible = "qcom,soundwire-v1.5.1";
2703 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2704 interrupt-names = "core";
2705 status = "disabled";
2706
2707 clocks = <&txmacro>;
2708 clock-names = "iface";
2709 label = "TX";
2710
2711 qcom,din-ports = <5>;
2712 qcom,dout-ports = <0>;
2713 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2714 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2715 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2716 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2717 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2718 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2719 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2720 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2721 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2722 #sound-dai-cells = <1>;
2723 #address-cells = <2>;
2724 #size-cells = <0>;
2725 };
2726
2727 aoncc: clock-controller@3380000 {
2728 compatible = "qcom,sm8250-lpass-aoncc";
2729 reg = <0 0x03380000 0 0x40000>;
2730 #clock-cells = <1>;
2731 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2732 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2733 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2734 clock-names = "core", "audio", "bus";
2735 };
2736
2737 lpass_tlmm: pinctrl@33c0000 {
2738 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2739 reg = <0 0x033c0000 0x0 0x20000>,
2740 <0 0x03550000 0x0 0x10000>;
2741 gpio-controller;
2742 #gpio-cells = <2>;
2743 gpio-ranges = <&lpass_tlmm 0 0 14>;
2744
2745 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2746 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2747 clock-names = "core", "audio";
2748
2749 wsa_swr_active: wsa-swr-active-state {
2750 clk-pins {
2751 pins = "gpio10";
2752 function = "wsa_swr_clk";
2753 drive-strength = <2>;
2754 slew-rate = <1>;
2755 bias-disable;
2756 };
2757
2758 data-pins {
2759 pins = "gpio11";
2760 function = "wsa_swr_data";
2761 drive-strength = <2>;
2762 slew-rate = <1>;
2763 bias-bus-hold;
2764 };
2765 };
2766
2767 wsa_swr_sleep: wsa-swr-sleep-state {
2768 clk-pins {
2769 pins = "gpio10";
2770 function = "wsa_swr_clk";
2771 drive-strength = <2>;
2772 bias-pull-down;
2773 };
2774
2775 data-pins {
2776 pins = "gpio11";
2777 function = "wsa_swr_data";
2778 drive-strength = <2>;
2779 bias-pull-down;
2780 };
2781 };
2782
2783 dmic01_active: dmic01-active-state {
2784 clk-pins {
2785 pins = "gpio6";
2786 function = "dmic1_clk";
2787 drive-strength = <8>;
2788 output-high;
2789 };
2790 data-pins {
2791 pins = "gpio7";
2792 function = "dmic1_data";
2793 drive-strength = <8>;
2794 };
2795 };
2796
2797 dmic01_sleep: dmic01-sleep-state {
2798 clk-pins {
2799 pins = "gpio6";
2800 function = "dmic1_clk";
2801 drive-strength = <2>;
2802 bias-disable;
2803 output-low;
2804 };
2805
2806 data-pins {
2807 pins = "gpio7";
2808 function = "dmic1_data";
2809 drive-strength = <2>;
2810 bias-pull-down;
2811 };
2812 };
2813
2814 rx_swr_active: rx-swr-active-state {
2815 clk-pins {
2816 pins = "gpio3";
2817 function = "swr_rx_clk";
2818 drive-strength = <2>;
2819 slew-rate = <1>;
2820 bias-disable;
2821 };
2822
2823 data-pins {
2824 pins = "gpio4", "gpio5";
2825 function = "swr_rx_data";
2826 drive-strength = <2>;
2827 slew-rate = <1>;
2828 bias-bus-hold;
2829 };
2830 };
2831
2832 tx_swr_active: tx-swr-active-state {
2833 clk-pins {
2834 pins = "gpio0";
2835 function = "swr_tx_clk";
2836 drive-strength = <2>;
2837 slew-rate = <1>;
2838 bias-disable;
2839 };
2840
2841 data-pins {
2842 pins = "gpio1", "gpio2";
2843 function = "swr_tx_data";
2844 drive-strength = <2>;
2845 slew-rate = <1>;
2846 bias-bus-hold;
2847 };
2848 };
2849
2850 tx_swr_sleep: tx-swr-sleep-state {
2851 clk-pins {
2852 pins = "gpio0";
2853 function = "swr_tx_clk";
2854 drive-strength = <2>;
2855 bias-pull-down;
2856 };
2857
2858 data1-pins {
2859 pins = "gpio1";
2860 function = "swr_tx_data";
2861 drive-strength = <2>;
2862 bias-bus-hold;
2863 };
2864
2865 data2-pins {
2866 pins = "gpio2";
2867 function = "swr_tx_data";
2868 drive-strength = <2>;
2869 bias-pull-down;
2870 };
2871 };
2872 };
2873
2874 gpu: gpu@3d00000 {
2875 compatible = "qcom,adreno-650.2",
2876 "qcom,adreno";
2877
2878 reg = <0 0x03d00000 0 0x40000>;
2879 reg-names = "kgsl_3d0_reg_memory";
2880
2881 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2882
2883 iommus = <&adreno_smmu 0 0x401>;
2884
2885 operating-points-v2 = <&gpu_opp_table>;
2886
2887 qcom,gmu = <&gmu>;
2888
2889 nvmem-cells = <&gpu_speed_bin>;
2890 nvmem-cell-names = "speed_bin";
2891
2892 status = "disabled";
2893
2894 zap-shader {
2895 memory-region = <&gpu_mem>;
2896 };
2897
2898 gpu_opp_table: opp-table {
2899 compatible = "operating-points-v2";
2900
2901 opp-670000000 {
2902 opp-hz = /bits/ 64 <670000000>;
2903 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2904 opp-supported-hw = <0xa>;
2905 };
2906
2907 opp-587000000 {
2908 opp-hz = /bits/ 64 <587000000>;
2909 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2910 opp-supported-hw = <0xb>;
2911 };
2912
2913 opp-525000000 {
2914 opp-hz = /bits/ 64 <525000000>;
2915 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2916 opp-supported-hw = <0xf>;
2917 };
2918
2919 opp-490000000 {
2920 opp-hz = /bits/ 64 <490000000>;
2921 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2922 opp-supported-hw = <0xf>;
2923 };
2924
2925 opp-441600000 {
2926 opp-hz = /bits/ 64 <441600000>;
2927 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2928 opp-supported-hw = <0xf>;
2929 };
2930
2931 opp-400000000 {
2932 opp-hz = /bits/ 64 <400000000>;
2933 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2934 opp-supported-hw = <0xf>;
2935 };
2936
2937 opp-305000000 {
2938 opp-hz = /bits/ 64 <305000000>;
2939 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2940 opp-supported-hw = <0xf>;
2941 };
2942 };
2943 };
2944
2945 gmu: gmu@3d6a000 {
2946 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2947
2948 reg = <0 0x03d6a000 0 0x30000>,
2949 <0 0x3de0000 0 0x10000>,
2950 <0 0xb290000 0 0x10000>,
2951 <0 0xb490000 0 0x10000>;
2952 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2953
2954 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2955 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2956 interrupt-names = "hfi", "gmu";
2957
2958 clocks = <&gpucc GPU_CC_AHB_CLK>,
2959 <&gpucc GPU_CC_CX_GMU_CLK>,
2960 <&gpucc GPU_CC_CXO_CLK>,
2961 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2962 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2963 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2964
2965 power-domains = <&gpucc GPU_CX_GDSC>,
2966 <&gpucc GPU_GX_GDSC>;
2967 power-domain-names = "cx", "gx";
2968
2969 iommus = <&adreno_smmu 5 0x400>;
2970
2971 operating-points-v2 = <&gmu_opp_table>;
2972
2973 status = "disabled";
2974
2975 gmu_opp_table: opp-table {
2976 compatible = "operating-points-v2";
2977
2978 opp-200000000 {
2979 opp-hz = /bits/ 64 <200000000>;
2980 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2981 };
2982 };
2983 };
2984
2985 gpucc: clock-controller@3d90000 {
2986 compatible = "qcom,sm8250-gpucc";
2987 reg = <0 0x03d90000 0 0x9000>;
2988 clocks = <&rpmhcc RPMH_CXO_CLK>,
2989 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2990 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2991 clock-names = "bi_tcxo",
2992 "gcc_gpu_gpll0_clk_src",
2993 "gcc_gpu_gpll0_div_clk_src";
2994 #clock-cells = <1>;
2995 #reset-cells = <1>;
2996 #power-domain-cells = <1>;
2997 };
2998
2999 adreno_smmu: iommu@3da0000 {
3000 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
3001 "qcom,smmu-500", "arm,mmu-500";
3002 reg = <0 0x03da0000 0 0x10000>;
3003 #iommu-cells = <2>;
3004 #global-interrupts = <2>;
3005 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3006 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3007 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3008 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3009 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3010 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3011 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3012 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3013 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3014 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3015 clocks = <&gpucc GPU_CC_AHB_CLK>,
3016 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3017 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3018 clock-names = "ahb", "bus", "iface";
3019
3020 power-domains = <&gpucc GPU_CX_GDSC>;
3021 dma-coherent;
3022 };
3023
3024 slpi: remoteproc@5c00000 {
3025 compatible = "qcom,sm8250-slpi-pas";
3026 reg = <0 0x05c00000 0 0x4000>;
3027
3028 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3029 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3030 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3031 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3032 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3033 interrupt-names = "wdog", "fatal", "ready",
3034 "handover", "stop-ack";
3035
3036 clocks = <&rpmhcc RPMH_CXO_CLK>;
3037 clock-names = "xo";
3038
3039 power-domains = <&rpmhpd RPMHPD_LCX>,
3040 <&rpmhpd RPMHPD_LMX>;
3041 power-domain-names = "lcx", "lmx";
3042
3043 memory-region = <&slpi_mem>;
3044
3045 qcom,qmp = <&aoss_qmp>;
3046
3047 qcom,smem-states = <&smp2p_slpi_out 0>;
3048 qcom,smem-state-names = "stop";
3049
3050 status = "disabled";
3051
3052 glink-edge {
3053 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3054 IPCC_MPROC_SIGNAL_GLINK_QMP
3055 IRQ_TYPE_EDGE_RISING>;
3056 mboxes = <&ipcc IPCC_CLIENT_SLPI
3057 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3058
3059 label = "slpi";
3060 qcom,remote-pid = <3>;
3061
3062 fastrpc {
3063 compatible = "qcom,fastrpc";
3064 qcom,glink-channels = "fastrpcglink-apps-dsp";
3065 label = "sdsp";
3066 qcom,non-secure-domain;
3067 #address-cells = <1>;
3068 #size-cells = <0>;
3069
3070 compute-cb@1 {
3071 compatible = "qcom,fastrpc-compute-cb";
3072 reg = <1>;
3073 iommus = <&apps_smmu 0x0541 0x0>;
3074 };
3075
3076 compute-cb@2 {
3077 compatible = "qcom,fastrpc-compute-cb";
3078 reg = <2>;
3079 iommus = <&apps_smmu 0x0542 0x0>;
3080 };
3081
3082 compute-cb@3 {
3083 compatible = "qcom,fastrpc-compute-cb";
3084 reg = <3>;
3085 iommus = <&apps_smmu 0x0543 0x0>;
3086 /* note: shared-cb = <4> in downstream */
3087 };
3088 };
3089 };
3090 };
3091
3092 stm@6002000 {
3093 compatible = "arm,coresight-stm", "arm,primecell";
3094 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3095 reg-names = "stm-base", "stm-stimulus-base";
3096
3097 clocks = <&aoss_qmp>;
3098 clock-names = "apb_pclk";
3099
3100 out-ports {
3101 port {
3102 stm_out: endpoint {
3103 remote-endpoint = <&funnel0_in7>;
3104 };
3105 };
3106 };
3107 };
3108
3109 tpda@6004000 {
3110 compatible = "qcom,coresight-tpda", "arm,primecell";
3111 reg = <0 0x06004000 0 0x1000>;
3112
3113 clocks = <&aoss_qmp>;
3114 clock-names = "apb_pclk";
3115
3116 out-ports {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3117
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3118 port {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3119 tpda_out_funnel_qatb: endpoint {
3120 remote-endpoint = <&funnel_qatb_in_tpda>;
3121 };
3122 };
3123 };
3124
3125 in-ports {
3126 #address-cells = <1>;
3127 #size-cells = <0>;
3128
3129 port@9 {
3130 reg = <9>;
3131 tpda_9_in_tpdm_mm: endpoint {
3132 remote-endpoint = <&tpdm_mm_out_tpda9>;
3133 };
3134 };
3135
3136 port@17 {
3137 reg = <23>;
3138 tpda_23_in_tpdm_prng: endpoint {
3139 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3140 };
3141 };
3142 };
3143 };
3144
3145 funnel@6005000 {
3146 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3147 reg = <0 0x06005000 0 0x1000>;
3148
3149 clocks = <&aoss_qmp>;
3150 clock-names = "apb_pclk";
3151
3152 out-ports {
3153 port {
3154 funnel_qatb_out_funnel_in0: endpoint {
3155 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3156 };
3157 };
3158 };
3159
3160 in-ports {
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3161 port {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3162 funnel_qatb_in_tpda: endpoint {
3163 remote-endpoint = <&tpda_out_funnel_qatb>;
3164 };
3165 };
3166 };
3167 };
3168
3169 funnel@6041000 {
3170 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3171 reg = <0 0x06041000 0 0x1000>;
3172
3173 clocks = <&aoss_qmp>;
3174 clock-names = "apb_pclk";
3175
3176 out-ports {
3177 port {
3178 funnel_in0_out_funnel_merg: endpoint {
3179 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3180 };
3181 };
3182 };
3183
3184 in-ports {
3185 #address-cells = <1>;
3186 #size-cells = <0>;
3187
3188 port@6 {
3189 reg = <6>;
3190 funnel_in0_in_funnel_qatb: endpoint {
3191 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3192 };
3193 };
3194
3195 port@7 {
3196 reg = <7>;
3197 funnel0_in7: endpoint {
3198 remote-endpoint = <&stm_out>;
3199 };
3200 };
3201 };
3202 };
3203
3204 funnel@6042000 {
3205 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3206 reg = <0 0x06042000 0 0x1000>;
3207
3208 clocks = <&aoss_qmp>;
3209 clock-names = "apb_pclk";
3210
3211 out-ports {
3212 port {
3213 funnel_in1_out_funnel_merg: endpoint {
3214 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3215 };
3216 };
3217 };
3218
3219 in-ports {
3220 #address-cells = <1>;
3221 #size-cells = <0>;
3222
3223 port@4 {
3224 reg = <4>;
3225 funnel_in1_in_funnel_apss_merg: endpoint {
3226 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3227 };
3228 };
3229 };
3230 };
3231
3232 funnel@6045000 {
3233 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3234 reg = <0 0x06045000 0 0x1000>;
3235
3236 clocks = <&aoss_qmp>;
3237 clock-names = "apb_pclk";
3238
3239 out-ports {
3240 port {
3241 funnel_merg_out_funnel_swao: endpoint {
3242 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3243 };
3244 };
3245 };
3246
3247 in-ports {
3248 #address-cells = <1>;
3249 #size-cells = <0>;
3250
3251 port@0 {
3252 reg = <0>;
3253 funnel_merg_in_funnel_in0: endpoint {
3254 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3255 };
3256 };
3257
3258 port@1 {
3259 reg = <1>;
3260 funnel_merg_in_funnel_in1: endpoint {
3261 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3262 };
3263 };
3264 };
3265 };
3266
3267 replicator@6046000 {
3268 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3269 reg = <0 0x06046000 0 0x1000>;
3270
3271 clocks = <&aoss_qmp>;
3272 clock-names = "apb_pclk";
3273
3274 out-ports {
3275 port {
3276 replicator_out: endpoint {
3277 remote-endpoint = <&etr_in>;
3278 };
3279 };
3280 };
3281
3282 in-ports {
3283 port {
3284 replicator_cx_in_swao_out: endpoint {
3285 remote-endpoint = <&replicator_swao_out_cx_in>;
3286 };
3287 };
3288 };
3289 };
3290
3291 etr@6048000 {
3292 compatible = "arm,coresight-tmc", "arm,primecell";
3293 reg = <0 0x06048000 0 0x1000>;
3294
3295 clocks = <&aoss_qmp>;
3296 clock-names = "apb_pclk";
3297 arm,scatter-gather;
3298
3299 in-ports {
3300 port {
3301 etr_in: endpoint {
3302 remote-endpoint = <&replicator_out>;
3303 };
3304 };
3305 };
3306 };
3307
3308 tpdm@684c000 {
3309 compatible = "qcom,coresight-tpdm", "arm,primecell";
3310 reg = <0 0x0684c000 0 0x1000>;
3311
3312 clocks = <&aoss_qmp>;
3313 clock-names = "apb_pclk";
3314
3315 out-ports {
3316 port {
3317 tpdm_prng_out_tpda_23: endpoint {
3318 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3319 };
3320 };
3321 };
3322 };
3323
3324 funnel@6b04000 {
3325 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3326 arm,primecell-periphid = <0x000bb908>;
3327
3328 reg = <0 0x06b04000 0 0x1000>;
3329
3330 clocks = <&aoss_qmp>;
3331 clock-names = "apb_pclk";
3332
3333 out-ports {
3334 port {
3335 funnel_swao_out_etf: endpoint {
3336 remote-endpoint = <&etf_in_funnel_swao_out>;
3337 };
3338 };
3339 };
3340
3341 in-ports {
3342 #address-cells = <1>;
3343 #size-cells = <0>;
3344
3345 port@7 {
3346 reg = <7>;
3347 funnel_swao_in_funnel_merg: endpoint {
3348 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3349 };
3350 };
3351 };
3352 };
3353
3354 etf@6b05000 {
3355 compatible = "arm,coresight-tmc", "arm,primecell";
3356 reg = <0 0x06b05000 0 0x1000>;
3357
3358 clocks = <&aoss_qmp>;
3359 clock-names = "apb_pclk";
3360
3361 out-ports {
3362 port {
3363 etf_out: endpoint {
3364 remote-endpoint = <&replicator_in>;
3365 };
3366 };
3367 };
3368
3369 in-ports {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3370
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3371 port {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3372 etf_in_funnel_swao_out: endpoint {
3373 remote-endpoint = <&funnel_swao_out_etf>;
3374 };
3375 };
3376 };
3377 };
3378
3379 replicator@6b06000 {
3380 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3381 reg = <0 0x06b06000 0 0x1000>;
3382
3383 clocks = <&aoss_qmp>;
3384 clock-names = "apb_pclk";
3385
3386 out-ports {
3387 port {
3388 replicator_swao_out_cx_in: endpoint {
3389 remote-endpoint = <&replicator_cx_in_swao_out>;
3390 };
3391 };
3392 };
3393
3394 in-ports {
3395 port {
3396 replicator_in: endpoint {
3397 remote-endpoint = <&etf_out>;
3398 };
3399 };
3400 };
3401 };
3402
3403 tpdm@6c08000 {
3404 compatible = "qcom,coresight-tpdm", "arm,primecell";
3405 reg = <0 0x06c08000 0 0x1000>;
3406
3407 clocks = <&aoss_qmp>;
3408 clock-names = "apb_pclk";
3409
3410 out-ports {
3411 port {
3412 tpdm_mm_out_funnel_dl_mm: endpoint {
3413 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3414 };
3415 };
3416 };
3417 };
3418
3419 funnel@6c0b000 {
3420 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3421 reg = <0 0x06c0b000 0 0x1000>;
3422
3423 clocks = <&aoss_qmp>;
3424 clock-names = "apb_pclk";
3425
3426 out-ports {
3427 port {
3428 funnel_dl_mm_out_funnel_dl_center: endpoint {
3429 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3430 };
3431 };
3432 };
3433
3434 in-ports {
3435 #address-cells = <1>;
3436 #size-cells = <0>;
3437
3438 port@3 {
3439 reg = <3>;
3440 funnel_dl_mm_in_tpdm_mm: endpoint {
3441 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3442 };
3443 };
3444 };
3445 };
3446
3447 funnel@6c2d000 {
3448 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3449 reg = <0 0x06c2d000 0 0x1000>;
3450
3451 clocks = <&aoss_qmp>;
3452 clock-names = "apb_pclk";
3453
3454 out-ports {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3455 port {
3456 tpdm_mm_out_tpda9: endpoint {
3457 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3458 };
3459 };
3460 };
3461
3462 in-ports {
3463 #address-cells = <1>;
3464 #size-cells = <0>;
3465
3466 port@2 {
3467 reg = <2>;
3468 funnel_dl_center_in_funnel_dl_mm: endpoint {
3469 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3470 };
3471 };
3472 };
3473 };
3474
3475 etm@7040000 {
3476 compatible = "arm,coresight-etm4x", "arm,primecell";
3477 reg = <0 0x07040000 0 0x1000>;
3478
3479 cpu = <&CPU0>;
3480
3481 clocks = <&aoss_qmp>;
3482 clock-names = "apb_pclk";
3483 arm,coresight-loses-context-with-cpu;
3484
3485 out-ports {
3486 port {
3487 etm0_out: endpoint {
3488 remote-endpoint = <&apss_funnel_in0>;
3489 };
3490 };
3491 };
3492 };
3493
3494 etm@7140000 {
3495 compatible = "arm,coresight-etm4x", "arm,primecell";
3496 reg = <0 0x07140000 0 0x1000>;
3497
3498 cpu = <&CPU1>;
3499
3500 clocks = <&aoss_qmp>;
3501 clock-names = "apb_pclk";
3502 arm,coresight-loses-context-with-cpu;
3503
3504 out-ports {
3505 port {
3506 etm1_out: endpoint {
3507 remote-endpoint = <&apss_funnel_in1>;
3508 };
3509 };
3510 };
3511 };
3512
3513 etm@7240000 {
3514 compatible = "arm,coresight-etm4x", "arm,primecell";
3515 reg = <0 0x07240000 0 0x1000>;
3516
3517 cpu = <&CPU2>;
3518
3519 clocks = <&aoss_qmp>;
3520 clock-names = "apb_pclk";
3521 arm,coresight-loses-context-with-cpu;
3522
3523 out-ports {
3524 port {
3525 etm2_out: endpoint {
3526 remote-endpoint = <&apss_funnel_in2>;
3527 };
3528 };
3529 };
3530 };
3531
3532 etm@7340000 {
3533 compatible = "arm,coresight-etm4x", "arm,primecell";
3534 reg = <0 0x07340000 0 0x1000>;
3535
3536 cpu = <&CPU3>;
3537
3538 clocks = <&aoss_qmp>;
3539 clock-names = "apb_pclk";
3540 arm,coresight-loses-context-with-cpu;
3541
3542 out-ports {
3543 port {
3544 etm3_out: endpoint {
3545 remote-endpoint = <&apss_funnel_in3>;
3546 };
3547 };
3548 };
3549 };
3550
3551 etm@7440000 {
3552 compatible = "arm,coresight-etm4x", "arm,primecell";
3553 reg = <0 0x07440000 0 0x1000>;
3554
3555 cpu = <&CPU4>;
3556
3557 clocks = <&aoss_qmp>;
3558 clock-names = "apb_pclk";
3559 arm,coresight-loses-context-with-cpu;
3560
3561 out-ports {
3562 port {
3563 etm4_out: endpoint {
3564 remote-endpoint = <&apss_funnel_in4>;
3565 };
3566 };
3567 };
3568 };
3569
3570 etm@7540000 {
3571 compatible = "arm,coresight-etm4x", "arm,primecell";
3572 reg = <0 0x07540000 0 0x1000>;
3573
3574 cpu = <&CPU5>;
3575
3576 clocks = <&aoss_qmp>;
3577 clock-names = "apb_pclk";
3578 arm,coresight-loses-context-with-cpu;
3579
3580 out-ports {
3581 port {
3582 etm5_out: endpoint {
3583 remote-endpoint = <&apss_funnel_in5>;
3584 };
3585 };
3586 };
3587 };
3588
3589 etm@7640000 {
3590 compatible = "arm,coresight-etm4x", "arm,primecell";
3591 reg = <0 0x07640000 0 0x1000>;
3592
3593 cpu = <&CPU6>;
3594
3595 clocks = <&aoss_qmp>;
3596 clock-names = "apb_pclk";
3597 arm,coresight-loses-context-with-cpu;
3598
3599 out-ports {
3600 port {
3601 etm6_out: endpoint {
3602 remote-endpoint = <&apss_funnel_in6>;
3603 };
3604 };
3605 };
3606 };
3607
3608 etm@7740000 {
3609 compatible = "arm,coresight-etm4x", "arm,primecell";
3610 reg = <0 0x07740000 0 0x1000>;
3611
3612 cpu = <&CPU7>;
3613
3614 clocks = <&aoss_qmp>;
3615 clock-names = "apb_pclk";
3616 arm,coresight-loses-context-with-cpu;
3617
3618 out-ports {
3619 port {
3620 etm7_out: endpoint {
3621 remote-endpoint = <&apss_funnel_in7>;
3622 };
3623 };
3624 };
3625 };
3626
3627 funnel@7800000 {
3628 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3629 reg = <0 0x07800000 0 0x1000>;
3630
3631 clocks = <&aoss_qmp>;
3632 clock-names = "apb_pclk";
3633
3634 out-ports {
3635 port {
3636 funnel_apss_out_funnel_apss_merg: endpoint {
3637 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3638 };
3639 };
3640 };
3641
3642 in-ports {
3643 #address-cells = <1>;
3644 #size-cells = <0>;
3645
3646 port@0 {
3647 reg = <0>;
3648 apss_funnel_in0: endpoint {
3649 remote-endpoint = <&etm0_out>;
3650 };
3651 };
3652
3653 port@1 {
3654 reg = <1>;
3655 apss_funnel_in1: endpoint {
3656 remote-endpoint = <&etm1_out>;
3657 };
3658 };
3659
3660 port@2 {
3661 reg = <2>;
3662 apss_funnel_in2: endpoint {
3663 remote-endpoint = <&etm2_out>;
3664 };
3665 };
3666
3667 port@3 {
3668 reg = <3>;
3669 apss_funnel_in3: endpoint {
3670 remote-endpoint = <&etm3_out>;
3671 };
3672 };
3673
3674 port@4 {
3675 reg = <4>;
3676 apss_funnel_in4: endpoint {
3677 remote-endpoint = <&etm4_out>;
3678 };
3679 };
3680
3681 port@5 {
3682 reg = <5>;
3683 apss_funnel_in5: endpoint {
3684 remote-endpoint = <&etm5_out>;
3685 };
3686 };
3687
3688 port@6 {
3689 reg = <6>;
3690 apss_funnel_in6: endpoint {
3691 remote-endpoint = <&etm6_out>;
3692 };
3693 };
3694
3695 port@7 {
3696 reg = <7>;
3697 apss_funnel_in7: endpoint {
3698 remote-endpoint = <&etm7_out>;
3699 };
3700 };
3701 };
3702 };
3703
3704 funnel@7810000 {
3705 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3706 reg = <0 0x07810000 0 0x1000>;
3707
3708 clocks = <&aoss_qmp>;
3709 clock-names = "apb_pclk";
3710
3711 out-ports {
3712 port {
3713 funnel_apss_merg_out_funnel_in1: endpoint {
3714 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3715 };
3716 };
3717 };
3718
3719 in-ports {
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3720 port {
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3721 funnel_apss_merg_in_funnel_apss: endpoint {
3722 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3723 };
3724 };
3725 };
3726 };
3727
3728 cdsp: remoteproc@8300000 {
3729 compatible = "qcom,sm8250-cdsp-pas";
3730 reg = <0 0x08300000 0 0x10000>;
3731
3732 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3733 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3734 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3735 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3736 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3737 interrupt-names = "wdog", "fatal", "ready",
3738 "handover", "stop-ack";
3739
3740 clocks = <&rpmhcc RPMH_CXO_CLK>;
3741 clock-names = "xo";
3742
3743 power-domains = <&rpmhpd RPMHPD_CX>;
3744
3745 memory-region = <&cdsp_mem>;
3746
3747 qcom,qmp = <&aoss_qmp>;
3748
3749 qcom,smem-states = <&smp2p_cdsp_out 0>;
3750 qcom,smem-state-names = "stop";
3751
3752 status = "disabled";
3753
3754 glink-edge {
3755 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3756 IPCC_MPROC_SIGNAL_GLINK_QMP
3757 IRQ_TYPE_EDGE_RISING>;
3758 mboxes = <&ipcc IPCC_CLIENT_CDSP
3759 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3760
3761 label = "cdsp";
3762 qcom,remote-pid = <5>;
3763
3764 fastrpc {
3765 compatible = "qcom,fastrpc";
3766 qcom,glink-channels = "fastrpcglink-apps-dsp";
3767 label = "cdsp";
3768 qcom,non-secure-domain;
3769 #address-cells = <1>;
3770 #size-cells = <0>;
3771
3772 compute-cb@1 {
3773 compatible = "qcom,fastrpc-compute-cb";
3774 reg = <1>;
3775 iommus = <&apps_smmu 0x1001 0x0460>;
3776 };
3777
3778 compute-cb@2 {
3779 compatible = "qcom,fastrpc-compute-cb";
3780 reg = <2>;
3781 iommus = <&apps_smmu 0x1002 0x0460>;
3782 };
3783
3784 compute-cb@3 {
3785 compatible = "qcom,fastrpc-compute-cb";
3786 reg = <3>;
3787 iommus = <&apps_smmu 0x1003 0x0460>;
3788 };
3789
3790 compute-cb@4 {
3791 compatible = "qcom,fastrpc-compute-cb";
3792 reg = <4>;
3793 iommus = <&apps_smmu 0x1004 0x0460>;
3794 };
3795
3796 compute-cb@5 {
3797 compatible = "qcom,fastrpc-compute-cb";
3798 reg = <5>;
3799 iommus = <&apps_smmu 0x1005 0x0460>;
3800 };
3801
3802 compute-cb@6 {
3803 compatible = "qcom,fastrpc-compute-cb";
3804 reg = <6>;
3805 iommus = <&apps_smmu 0x1006 0x0460>;
3806 };
3807
3808 compute-cb@7 {
3809 compatible = "qcom,fastrpc-compute-cb";
3810 reg = <7>;
3811 iommus = <&apps_smmu 0x1007 0x0460>;
3812 };
3813
3814 compute-cb@8 {
3815 compatible = "qcom,fastrpc-compute-cb";
3816 reg = <8>;
3817 iommus = <&apps_smmu 0x1008 0x0460>;
3818 };
3819
3820 /* note: secure cb9 in downstream */
3821 };
3822 };
3823 };
3824
3825 usb_1_hsphy: phy@88e3000 {
3826 compatible = "qcom,sm8250-usb-hs-phy",
3827 "qcom,usb-snps-hs-7nm-phy";
3828 reg = <0 0x088e3000 0 0x400>;
3829 status = "disabled";
3830 #phy-cells = <0>;
3831
3832 clocks = <&rpmhcc RPMH_CXO_CLK>;
3833 clock-names = "ref";
3834
3835 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3836 };
3837
3838 usb_2_hsphy: phy@88e4000 {
3839 compatible = "qcom,sm8250-usb-hs-phy",
3840 "qcom,usb-snps-hs-7nm-phy";
3841 reg = <0 0x088e4000 0 0x400>;
3842 status = "disabled";
3843 #phy-cells = <0>;
3844
3845 clocks = <&rpmhcc RPMH_CXO_CLK>;
3846 clock-names = "ref";
3847
3848 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3849 };
3850
3851 usb_1_qmpphy: phy@88e8000 {
3852 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3853 reg = <0 0x088e8000 0 0x3000>;
3854 status = "disabled";
3855
3856 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3857 <&rpmhcc RPMH_CXO_CLK>,
3858 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3859 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3860 clock-names = "aux",
3861 "ref",
3862 "com_aux",
3863 "usb3_pipe";
3864
3865 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3866 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3867 reset-names = "phy", "common";
3868
3869 #clock-cells = <1>;
3870 #phy-cells = <1>;
3871
3872 ports {
3873 #address-cells = <1>;
3874 #size-cells = <0>;
3875
3876 port@0 {
3877 reg = <0>;
3878 usb_1_qmpphy_out: endpoint {};
3879 };
3880
3881 port@1 {
3882 reg = <1>;
3883 };
3884
3885 port@2 {
3886 reg = <2>;
3887
3888 usb_1_qmpphy_dp_in: endpoint {};
3889 };
3890 };
3891 };
3892
3893 usb_2_qmpphy: phy@88eb000 {
3894 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3895 reg = <0 0x088eb000 0 0x1000>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3896
3897 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3898 <&gcc GCC_USB3_SEC_CLKREF_EN>,
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3899 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3900 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3901 clock-names = "aux",
3902 "ref",
3903 "com_aux",
3904 "pipe";
3905 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3906 #clock-cells = <0>;
3907 #phy-cells = <0>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3908
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3909 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3910 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
3911 reset-names = "phy",
3912 "phy_phy";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3913
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]3914 status = "disabled";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]3915 };
3916
3917 sdhc_2: mmc@8804000 {
3918 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3919 reg = <0 0x08804000 0 0x1000>;
3920
3921 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3922 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3923 interrupt-names = "hc_irq", "pwr_irq";
3924
3925 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3926 <&gcc GCC_SDCC2_APPS_CLK>,
3927 <&rpmhcc RPMH_CXO_CLK>;
3928 clock-names = "iface", "core", "xo";
3929 iommus = <&apps_smmu 0x4a0 0x0>;
3930 qcom,dll-config = <0x0007642c>;
3931 qcom,ddr-config = <0x80040868>;
3932 power-domains = <&rpmhpd RPMHPD_CX>;
3933 operating-points-v2 = <&sdhc2_opp_table>;
3934
3935 status = "disabled";
3936
3937 sdhc2_opp_table: opp-table {
3938 compatible = "operating-points-v2";
3939
3940 opp-19200000 {
3941 opp-hz = /bits/ 64 <19200000>;
3942 required-opps = <&rpmhpd_opp_min_svs>;
3943 };
3944
3945 opp-50000000 {
3946 opp-hz = /bits/ 64 <50000000>;
3947 required-opps = <&rpmhpd_opp_low_svs>;
3948 };
3949
3950 opp-100000000 {
3951 opp-hz = /bits/ 64 <100000000>;
3952 required-opps = <&rpmhpd_opp_svs>;
3953 };
3954
3955 opp-202000000 {
3956 opp-hz = /bits/ 64 <202000000>;
3957 required-opps = <&rpmhpd_opp_svs_l1>;
3958 };
3959 };
3960 };
3961
3962 pmu@9091000 {
3963 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3964 reg = <0 0x09091000 0 0x1000>;
3965
3966 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3967
3968 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>;
3969
3970 operating-points-v2 = <&llcc_bwmon_opp_table>;
3971
3972 llcc_bwmon_opp_table: opp-table {
3973 compatible = "operating-points-v2";
3974
3975 opp-800000 {
3976 opp-peak-kBps = <(200 * 4 * 1000)>;
3977 };
3978
3979 opp-1200000 {
3980 opp-peak-kBps = <(300 * 4 * 1000)>;
3981 };
3982
3983 opp-1804000 {
3984 opp-peak-kBps = <(451 * 4 * 1000)>;
3985 };
3986
3987 opp-2188000 {
3988 opp-peak-kBps = <(547 * 4 * 1000)>;
3989 };
3990
3991 opp-2724000 {
3992 opp-peak-kBps = <(681 * 4 * 1000)>;
3993 };
3994
3995 opp-3072000 {
3996 opp-peak-kBps = <(768 * 4 * 1000)>;
3997 };
3998
3999 opp-4068000 {
4000 opp-peak-kBps = <(1017 * 4 * 1000)>;
4001 };
4002
4003 /* 1353 MHz, LPDDR4X */
4004
4005 opp-6220000 {
4006 opp-peak-kBps = <(1555 * 4 * 1000)>;
4007 };
4008
4009 opp-7216000 {
4010 opp-peak-kBps = <(1804 * 4 * 1000)>;
4011 };
4012
4013 opp-8368000 {
4014 opp-peak-kBps = <(2092 * 4 * 1000)>;
4015 };
4016
4017 /* LPDDR5 */
4018 opp-10944000 {
4019 opp-peak-kBps = <(2736 * 4 * 1000)>;
4020 };
4021 };
4022 };
4023
4024 pmu@90b6400 {
4025 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
4026 reg = <0 0x090b6400 0 0x600>;
4027
4028 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
4029
4030 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>;
4031 operating-points-v2 = <&cpu_bwmon_opp_table>;
4032
4033 cpu_bwmon_opp_table: opp-table {
4034 compatible = "operating-points-v2";
4035
4036 opp-800000 {
4037 opp-peak-kBps = <(200 * 4 * 1000)>;
4038 };
4039
4040 opp-1804000 {
4041 opp-peak-kBps = <(451 * 4 * 1000)>;
4042 };
4043
4044 opp-2188000 {
4045 opp-peak-kBps = <(547 * 4 * 1000)>;
4046 };
4047
4048 opp-2724000 {
4049 opp-peak-kBps = <(681 * 4 * 1000)>;
4050 };
4051
4052 opp-3072000 {
4053 opp-peak-kBps = <(768 * 4 * 1000)>;
4054 };
4055
4056 /* 1017MHz, 1353 MHz, LPDDR4X */
4057
4058 opp-6220000 {
4059 opp-peak-kBps = <(1555 * 4 * 1000)>;
4060 };
4061
4062 opp-6832000 {
4063 opp-peak-kBps = <(1708 * 4 * 1000)>;
4064 };
4065
4066 opp-8368000 {
4067 opp-peak-kBps = <(2092 * 4 * 1000)>;
4068 };
4069
4070 /* 2133MHz, LPDDR4X */
4071
4072 /* LPDDR5 */
4073 opp-10944000 {
4074 opp-peak-kBps = <(2736 * 4 * 1000)>;
4075 };
4076
4077 /* LPDDR5 */
4078 opp-12784000 {
4079 opp-peak-kBps = <(3196 * 4 * 1000)>;
4080 };
4081 };
4082 };
4083
4084 dc_noc: interconnect@90c0000 {
4085 compatible = "qcom,sm8250-dc-noc";
4086 reg = <0 0x090c0000 0 0x4200>;
4087 #interconnect-cells = <2>;
4088 qcom,bcm-voters = <&apps_bcm_voter>;
4089 };
4090
4091 gem_noc: interconnect@9100000 {
4092 compatible = "qcom,sm8250-gem-noc";
4093 reg = <0 0x09100000 0 0xb4000>;
4094 #interconnect-cells = <2>;
4095 qcom,bcm-voters = <&apps_bcm_voter>;
4096 };
4097
4098 npu_noc: interconnect@9990000 {
4099 compatible = "qcom,sm8250-npu-noc";
4100 reg = <0 0x09990000 0 0x1600>;
4101 #interconnect-cells = <2>;
4102 qcom,bcm-voters = <&apps_bcm_voter>;
4103 };
4104
4105 usb_1: usb@a6f8800 {
4106 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4107 reg = <0 0x0a6f8800 0 0x400>;
4108 status = "disabled";
4109 #address-cells = <2>;
4110 #size-cells = <2>;
4111 ranges;
4112 dma-ranges;
4113
4114 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4115 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4116 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4117 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4118 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4119 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4120 clock-names = "cfg_noc",
4121 "core",
4122 "iface",
4123 "sleep",
4124 "mock_utmi",
4125 "xo";
4126
4127 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4128 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4129 assigned-clock-rates = <19200000>, <200000000>;
4130
4131 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4132 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4133 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4134 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4135 interrupt-names = "hs_phy_irq",
4136 "ss_phy_irq",
4137 "dm_hs_phy_irq",
4138 "dp_hs_phy_irq";
4139
4140 power-domains = <&gcc USB30_PRIM_GDSC>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]4141 wakeup-source;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4142
4143 resets = <&gcc GCC_USB30_PRIM_BCR>;
4144
4145 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
4146 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
4147 interconnect-names = "usb-ddr", "apps-usb";
4148
4149 usb_1_dwc3: usb@a600000 {
4150 compatible = "snps,dwc3";
4151 reg = <0 0x0a600000 0 0xcd00>;
4152 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4153 iommus = <&apps_smmu 0x0 0x0>;
4154 snps,dis_u2_susphy_quirk;
4155 snps,dis_enblslpm_quirk;
4156 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4157 phy-names = "usb2-phy", "usb3-phy";
4158
4159 port {
4160 usb_1_role_switch_out: endpoint {};
4161 };
4162 };
4163 };
4164
4165 system-cache-controller@9200000 {
4166 compatible = "qcom,sm8250-llcc";
4167 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
4168 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
4169 <0 0x09600000 0 0x50000>;
4170 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4171 "llcc3_base", "llcc_broadcast_base";
4172 };
4173
4174 usb_2: usb@a8f8800 {
4175 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4176 reg = <0 0x0a8f8800 0 0x400>;
4177 status = "disabled";
4178 #address-cells = <2>;
4179 #size-cells = <2>;
4180 ranges;
4181 dma-ranges;
4182
4183 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4184 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4185 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4186 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4187 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4189 clock-names = "cfg_noc",
4190 "core",
4191 "iface",
4192 "sleep",
4193 "mock_utmi",
4194 "xo";
4195
4196 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4197 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4198 assigned-clock-rates = <19200000>, <200000000>;
4199
4200 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4201 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
4202 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4203 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
4204 interrupt-names = "hs_phy_irq",
4205 "ss_phy_irq",
4206 "dm_hs_phy_irq",
4207 "dp_hs_phy_irq";
4208
4209 power-domains = <&gcc USB30_SEC_GDSC>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]4210 wakeup-source;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4211
4212 resets = <&gcc GCC_USB30_SEC_BCR>;
4213
4214 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
4215 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
4216 interconnect-names = "usb-ddr", "apps-usb";
4217
4218 usb_2_dwc3: usb@a800000 {
4219 compatible = "snps,dwc3";
4220 reg = <0 0x0a800000 0 0xcd00>;
4221 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4222 iommus = <&apps_smmu 0x20 0>;
4223 snps,dis_u2_susphy_quirk;
4224 snps,dis_enblslpm_quirk;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]4225 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]4226 phy-names = "usb2-phy", "usb3-phy";
4227 };
4228 };
4229
4230 venus: video-codec@aa00000 {
4231 compatible = "qcom,sm8250-venus";
4232 reg = <0 0x0aa00000 0 0x100000>;
4233 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4234 power-domains = <&videocc MVS0C_GDSC>,
4235 <&videocc MVS0_GDSC>,
4236 <&rpmhpd RPMHPD_MX>;
4237 power-domain-names = "venus", "vcodec0", "mx";
4238 operating-points-v2 = <&venus_opp_table>;
4239
4240 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4241 <&videocc VIDEO_CC_MVS0C_CLK>,
4242 <&videocc VIDEO_CC_MVS0_CLK>;
4243 clock-names = "iface", "core", "vcodec0_core";
4244
4245 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
4246 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
4247 interconnect-names = "cpu-cfg", "video-mem";
4248
4249 iommus = <&apps_smmu 0x2100 0x0400>;
4250 memory-region = <&video_mem>;
4251
4252 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4253 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4254 reset-names = "bus", "core";
4255
4256 status = "disabled";
4257
4258 video-decoder {
4259 compatible = "venus-decoder";
4260 };
4261
4262 video-encoder {
4263 compatible = "venus-encoder";
4264 };
4265
4266 venus_opp_table: opp-table {
4267 compatible = "operating-points-v2";
4268
4269 opp-720000000 {
4270 opp-hz = /bits/ 64 <720000000>;
4271 required-opps = <&rpmhpd_opp_low_svs>;
4272 };
4273
4274 opp-1014000000 {
4275 opp-hz = /bits/ 64 <1014000000>;
4276 required-opps = <&rpmhpd_opp_svs>;
4277 };
4278
4279 opp-1098000000 {
4280 opp-hz = /bits/ 64 <1098000000>;
4281 required-opps = <&rpmhpd_opp_svs_l1>;
4282 };
4283
4284 opp-1332000000 {
4285 opp-hz = /bits/ 64 <1332000000>;
4286 required-opps = <&rpmhpd_opp_nom>;
4287 };
4288 };
4289 };
4290
4291 videocc: clock-controller@abf0000 {
4292 compatible = "qcom,sm8250-videocc";
4293 reg = <0 0x0abf0000 0 0x10000>;
4294 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4295 <&rpmhcc RPMH_CXO_CLK>,
4296 <&rpmhcc RPMH_CXO_CLK_A>;
4297 power-domains = <&rpmhpd RPMHPD_MMCX>;
4298 required-opps = <&rpmhpd_opp_low_svs>;
4299 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4300 #clock-cells = <1>;
4301 #reset-cells = <1>;
4302 #power-domain-cells = <1>;
4303 };
4304
4305 cci0: cci@ac4f000 {
4306 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4307 #address-cells = <1>;
4308 #size-cells = <0>;
4309
4310 reg = <0 0x0ac4f000 0 0x1000>;
4311 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4312 power-domains = <&camcc TITAN_TOP_GDSC>;
4313
4314 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4315 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4316 <&camcc CAM_CC_CPAS_AHB_CLK>,
4317 <&camcc CAM_CC_CCI_0_CLK>,
4318 <&camcc CAM_CC_CCI_0_CLK_SRC>;
4319 clock-names = "camnoc_axi",
4320 "slow_ahb_src",
4321 "cpas_ahb",
4322 "cci",
4323 "cci_src";
4324
4325 pinctrl-0 = <&cci0_default>;
4326 pinctrl-1 = <&cci0_sleep>;
4327 pinctrl-names = "default", "sleep";
4328
4329 status = "disabled";
4330
4331 cci0_i2c0: i2c-bus@0 {
4332 reg = <0>;
4333 clock-frequency = <1000000>;
4334 #address-cells = <1>;
4335 #size-cells = <0>;
4336 };
4337
4338 cci0_i2c1: i2c-bus@1 {
4339 reg = <1>;
4340 clock-frequency = <1000000>;
4341 #address-cells = <1>;
4342 #size-cells = <0>;
4343 };
4344 };
4345
4346 cci1: cci@ac50000 {
4347 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4348 #address-cells = <1>;
4349 #size-cells = <0>;
4350
4351 reg = <0 0x0ac50000 0 0x1000>;
4352 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4353 power-domains = <&camcc TITAN_TOP_GDSC>;
4354
4355 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4356 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4357 <&camcc CAM_CC_CPAS_AHB_CLK>,
4358 <&camcc CAM_CC_CCI_1_CLK>,
4359 <&camcc CAM_CC_CCI_1_CLK_SRC>;
4360 clock-names = "camnoc_axi",
4361 "slow_ahb_src",
4362 "cpas_ahb",
4363 "cci",
4364 "cci_src";
4365
4366 pinctrl-0 = <&cci1_default>;
4367 pinctrl-1 = <&cci1_sleep>;
4368 pinctrl-names = "default", "sleep";
4369
4370 status = "disabled";
4371
4372 cci1_i2c0: i2c-bus@0 {
4373 reg = <0>;
4374 clock-frequency = <1000000>;
4375 #address-cells = <1>;
4376 #size-cells = <0>;
4377 };
4378
4379 cci1_i2c1: i2c-bus@1 {
4380 reg = <1>;
4381 clock-frequency = <1000000>;
4382 #address-cells = <1>;
4383 #size-cells = <0>;
4384 };
4385 };
4386
4387 camss: camss@ac6a000 {
4388 compatible = "qcom,sm8250-camss";
4389 status = "disabled";
4390
4391 reg = <0 0x0ac6a000 0 0x2000>,
4392 <0 0x0ac6c000 0 0x2000>,
4393 <0 0x0ac6e000 0 0x1000>,
4394 <0 0x0ac70000 0 0x1000>,
4395 <0 0x0ac72000 0 0x1000>,
4396 <0 0x0ac74000 0 0x1000>,
4397 <0 0x0acb4000 0 0xd000>,
4398 <0 0x0acc3000 0 0xd000>,
4399 <0 0x0acd9000 0 0x2200>,
4400 <0 0x0acdb200 0 0x2200>;
4401 reg-names = "csiphy0",
4402 "csiphy1",
4403 "csiphy2",
4404 "csiphy3",
4405 "csiphy4",
4406 "csiphy5",
4407 "vfe0",
4408 "vfe1",
4409 "vfe_lite0",
4410 "vfe_lite1";
4411
4412 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4413 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4414 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4415 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4416 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4417 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4418 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4419 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4420 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4421 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4422 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4423 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4424 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4425 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4426 interrupt-names = "csiphy0",
4427 "csiphy1",
4428 "csiphy2",
4429 "csiphy3",
4430 "csiphy4",
4431 "csiphy5",
4432 "csid0",
4433 "csid1",
4434 "csid2",
4435 "csid3",
4436 "vfe0",
4437 "vfe1",
4438 "vfe_lite0",
4439 "vfe_lite1";
4440
4441 power-domains = <&camcc IFE_0_GDSC>,
4442 <&camcc IFE_1_GDSC>,
4443 <&camcc TITAN_TOP_GDSC>;
4444
4445 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4446 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4447 <&gcc GCC_CAMERA_SF_AXI_CLK>,
4448 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4449 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4450 <&camcc CAM_CC_CORE_AHB_CLK>,
4451 <&camcc CAM_CC_CPAS_AHB_CLK>,
4452 <&camcc CAM_CC_CSIPHY0_CLK>,
4453 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4454 <&camcc CAM_CC_CSIPHY1_CLK>,
4455 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4456 <&camcc CAM_CC_CSIPHY2_CLK>,
4457 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4458 <&camcc CAM_CC_CSIPHY3_CLK>,
4459 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4460 <&camcc CAM_CC_CSIPHY4_CLK>,
4461 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4462 <&camcc CAM_CC_CSIPHY5_CLK>,
4463 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4464 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4465 <&camcc CAM_CC_IFE_0_AHB_CLK>,
4466 <&camcc CAM_CC_IFE_0_AXI_CLK>,
4467 <&camcc CAM_CC_IFE_0_CLK>,
4468 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4469 <&camcc CAM_CC_IFE_0_CSID_CLK>,
4470 <&camcc CAM_CC_IFE_0_AREG_CLK>,
4471 <&camcc CAM_CC_IFE_1_AHB_CLK>,
4472 <&camcc CAM_CC_IFE_1_AXI_CLK>,
4473 <&camcc CAM_CC_IFE_1_CLK>,
4474 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4475 <&camcc CAM_CC_IFE_1_CSID_CLK>,
4476 <&camcc CAM_CC_IFE_1_AREG_CLK>,
4477 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4478 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4479 <&camcc CAM_CC_IFE_LITE_CLK>,
4480 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4481 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4482
4483 clock-names = "cam_ahb_clk",
4484 "cam_hf_axi",
4485 "cam_sf_axi",
4486 "camnoc_axi",
4487 "camnoc_axi_src",
4488 "core_ahb",
4489 "cpas_ahb",
4490 "csiphy0",
4491 "csiphy0_timer",
4492 "csiphy1",
4493 "csiphy1_timer",
4494 "csiphy2",
4495 "csiphy2_timer",
4496 "csiphy3",
4497 "csiphy3_timer",
4498 "csiphy4",
4499 "csiphy4_timer",
4500 "csiphy5",
4501 "csiphy5_timer",
4502 "slow_ahb_src",
4503 "vfe0_ahb",
4504 "vfe0_axi",
4505 "vfe0",
4506 "vfe0_cphy_rx",
4507 "vfe0_csid",
4508 "vfe0_areg",
4509 "vfe1_ahb",
4510 "vfe1_axi",
4511 "vfe1",
4512 "vfe1_cphy_rx",
4513 "vfe1_csid",
4514 "vfe1_areg",
4515 "vfe_lite_ahb",
4516 "vfe_lite_axi",
4517 "vfe_lite",
4518 "vfe_lite_cphy_rx",
4519 "vfe_lite_csid";
4520
4521 iommus = <&apps_smmu 0x800 0x400>,
4522 <&apps_smmu 0x801 0x400>,
4523 <&apps_smmu 0x840 0x400>,
4524 <&apps_smmu 0x841 0x400>,
4525 <&apps_smmu 0xc00 0x400>,
4526 <&apps_smmu 0xc01 0x400>,
4527 <&apps_smmu 0xc40 0x400>,
4528 <&apps_smmu 0xc41 0x400>;
4529
4530 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4531 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4532 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4533 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4534 interconnect-names = "cam_ahb",
4535 "cam_hf_0_mnoc",
4536 "cam_sf_0_mnoc",
4537 "cam_sf_icp_mnoc";
4538
4539 ports {
4540 #address-cells = <1>;
4541 #size-cells = <0>;
4542
4543 port@0 {
4544 reg = <0>;
4545 };
4546
4547 port@1 {
4548 reg = <1>;
4549 };
4550
4551 port@2 {
4552 reg = <2>;
4553 };
4554
4555 port@3 {
4556 reg = <3>;
4557 };
4558
4559 port@4 {
4560 reg = <4>;
4561 };
4562
4563 port@5 {
4564 reg = <5>;
4565 };
4566 };
4567 };
4568
4569 camcc: clock-controller@ad00000 {
4570 compatible = "qcom,sm8250-camcc";
4571 reg = <0 0x0ad00000 0 0x10000>;
4572 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4573 <&rpmhcc RPMH_CXO_CLK>,
4574 <&rpmhcc RPMH_CXO_CLK_A>,
4575 <&sleep_clk>;
4576 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4577 power-domains = <&rpmhpd RPMHPD_MMCX>;
4578 required-opps = <&rpmhpd_opp_low_svs>;
4579 status = "disabled";
4580 #clock-cells = <1>;
4581 #reset-cells = <1>;
4582 #power-domain-cells = <1>;
4583 };
4584
4585 mdss: display-subsystem@ae00000 {
4586 compatible = "qcom,sm8250-mdss";
4587 reg = <0 0x0ae00000 0 0x1000>;
4588 reg-names = "mdss";
4589
4590 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4591 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4592 interconnect-names = "mdp0-mem", "mdp1-mem";
4593
4594 power-domains = <&dispcc MDSS_GDSC>;
4595
4596 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4597 <&gcc GCC_DISP_HF_AXI_CLK>,
4598 <&gcc GCC_DISP_SF_AXI_CLK>,
4599 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4600 clock-names = "iface", "bus", "nrt_bus", "core";
4601
4602 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4603 interrupt-controller;
4604 #interrupt-cells = <1>;
4605
4606 iommus = <&apps_smmu 0x820 0x402>;
4607
4608 status = "disabled";
4609
4610 #address-cells = <2>;
4611 #size-cells = <2>;
4612 ranges;
4613
4614 mdss_mdp: display-controller@ae01000 {
4615 compatible = "qcom,sm8250-dpu";
4616 reg = <0 0x0ae01000 0 0x8f000>,
4617 <0 0x0aeb0000 0 0x2008>;
4618 reg-names = "mdp", "vbif";
4619
4620 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4621 <&gcc GCC_DISP_HF_AXI_CLK>,
4622 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4623 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4624 clock-names = "iface", "bus", "core", "vsync";
4625
4626 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4627 assigned-clock-rates = <19200000>;
4628
4629 operating-points-v2 = <&mdp_opp_table>;
4630 power-domains = <&rpmhpd RPMHPD_MMCX>;
4631
4632 interrupt-parent = <&mdss>;
4633 interrupts = <0>;
4634
4635 ports {
4636 #address-cells = <1>;
4637 #size-cells = <0>;
4638
4639 port@0 {
4640 reg = <0>;
4641 dpu_intf1_out: endpoint {
4642 remote-endpoint = <&mdss_dsi0_in>;
4643 };
4644 };
4645
4646 port@1 {
4647 reg = <1>;
4648 dpu_intf2_out: endpoint {
4649 remote-endpoint = <&mdss_dsi1_in>;
4650 };
4651 };
4652
4653 port@2 {
4654 reg = <2>;
4655
4656 dpu_intf0_out: endpoint {
4657 remote-endpoint = <&mdss_dp_in>;
4658 };
4659 };
4660 };
4661
4662 mdp_opp_table: opp-table {
4663 compatible = "operating-points-v2";
4664
4665 opp-200000000 {
4666 opp-hz = /bits/ 64 <200000000>;
4667 required-opps = <&rpmhpd_opp_low_svs>;
4668 };
4669
4670 opp-300000000 {
4671 opp-hz = /bits/ 64 <300000000>;
4672 required-opps = <&rpmhpd_opp_svs>;
4673 };
4674
4675 opp-345000000 {
4676 opp-hz = /bits/ 64 <345000000>;
4677 required-opps = <&rpmhpd_opp_svs_l1>;
4678 };
4679
4680 opp-460000000 {
4681 opp-hz = /bits/ 64 <460000000>;
4682 required-opps = <&rpmhpd_opp_nom>;
4683 };
4684 };
4685 };
4686
4687 mdss_dp: displayport-controller@ae90000 {
4688 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp";
4689 reg = <0 0xae90000 0 0x200>,
4690 <0 0xae90200 0 0x200>,
4691 <0 0xae90400 0 0x600>,
4692 <0 0xae91000 0 0x400>,
4693 <0 0xae91400 0 0x400>;
4694 interrupt-parent = <&mdss>;
4695 interrupts = <12>;
4696 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4697 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4698 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4699 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4700 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4701 clock-names = "core_iface",
4702 "core_aux",
4703 "ctrl_link",
4704 "ctrl_link_iface",
4705 "stream_pixel";
4706
4707 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4708 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4709 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4710 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4711
4712 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4713 phy-names = "dp";
4714
4715 #sound-dai-cells = <0>;
4716
4717 operating-points-v2 = <&dp_opp_table>;
4718 power-domains = <&rpmhpd SM8250_MMCX>;
4719
4720 status = "disabled";
4721
4722 ports {
4723 #address-cells = <1>;
4724 #size-cells = <0>;
4725
4726 port@0 {
4727 reg = <0>;
4728 mdss_dp_in: endpoint {
4729 remote-endpoint = <&dpu_intf0_out>;
4730 };
4731 };
4732
4733 port@1 {
4734 reg = <1>;
4735
4736 mdss_dp_out: endpoint {
4737 };
4738 };
4739 };
4740
4741 dp_opp_table: opp-table {
4742 compatible = "operating-points-v2";
4743
4744 opp-160000000 {
4745 opp-hz = /bits/ 64 <160000000>;
4746 required-opps = <&rpmhpd_opp_low_svs>;
4747 };
4748
4749 opp-270000000 {
4750 opp-hz = /bits/ 64 <270000000>;
4751 required-opps = <&rpmhpd_opp_svs>;
4752 };
4753
4754 opp-540000000 {
4755 opp-hz = /bits/ 64 <540000000>;
4756 required-opps = <&rpmhpd_opp_svs_l1>;
4757 };
4758
4759 opp-810000000 {
4760 opp-hz = /bits/ 64 <810000000>;
4761 required-opps = <&rpmhpd_opp_nom>;
4762 };
4763 };
4764 };
4765
4766 mdss_dsi0: dsi@ae94000 {
4767 compatible = "qcom,sm8250-dsi-ctrl",
4768 "qcom,mdss-dsi-ctrl";
4769 reg = <0 0x0ae94000 0 0x400>;
4770 reg-names = "dsi_ctrl";
4771
4772 interrupt-parent = <&mdss>;
4773 interrupts = <4>;
4774
4775 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4776 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4777 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4778 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4779 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4780 <&gcc GCC_DISP_HF_AXI_CLK>;
4781 clock-names = "byte",
4782 "byte_intf",
4783 "pixel",
4784 "core",
4785 "iface",
4786 "bus";
4787
4788 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4789 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4790
4791 operating-points-v2 = <&dsi_opp_table>;
4792 power-domains = <&rpmhpd RPMHPD_MMCX>;
4793
4794 phys = <&mdss_dsi0_phy>;
4795
4796 status = "disabled";
4797
4798 #address-cells = <1>;
4799 #size-cells = <0>;
4800
4801 ports {
4802 #address-cells = <1>;
4803 #size-cells = <0>;
4804
4805 port@0 {
4806 reg = <0>;
4807 mdss_dsi0_in: endpoint {
4808 remote-endpoint = <&dpu_intf1_out>;
4809 };
4810 };
4811
4812 port@1 {
4813 reg = <1>;
4814 mdss_dsi0_out: endpoint {
4815 };
4816 };
4817 };
4818
4819 dsi_opp_table: opp-table {
4820 compatible = "operating-points-v2";
4821
4822 opp-187500000 {
4823 opp-hz = /bits/ 64 <187500000>;
4824 required-opps = <&rpmhpd_opp_low_svs>;
4825 };
4826
4827 opp-300000000 {
4828 opp-hz = /bits/ 64 <300000000>;
4829 required-opps = <&rpmhpd_opp_svs>;
4830 };
4831
4832 opp-358000000 {
4833 opp-hz = /bits/ 64 <358000000>;
4834 required-opps = <&rpmhpd_opp_svs_l1>;
4835 };
4836 };
4837 };
4838
4839 mdss_dsi0_phy: phy@ae94400 {
4840 compatible = "qcom,dsi-phy-7nm";
4841 reg = <0 0x0ae94400 0 0x200>,
4842 <0 0x0ae94600 0 0x280>,
4843 <0 0x0ae94900 0 0x260>;
4844 reg-names = "dsi_phy",
4845 "dsi_phy_lane",
4846 "dsi_pll";
4847
4848 #clock-cells = <1>;
4849 #phy-cells = <0>;
4850
4851 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&rpmhcc RPMH_CXO_CLK>;
4853 clock-names = "iface", "ref";
4854
4855 status = "disabled";
4856 };
4857
4858 mdss_dsi1: dsi@ae96000 {
4859 compatible = "qcom,sm8250-dsi-ctrl",
4860 "qcom,mdss-dsi-ctrl";
4861 reg = <0 0x0ae96000 0 0x400>;
4862 reg-names = "dsi_ctrl";
4863
4864 interrupt-parent = <&mdss>;
4865 interrupts = <5>;
4866
4867 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4868 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4869 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4870 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4871 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4872 <&gcc GCC_DISP_HF_AXI_CLK>;
4873 clock-names = "byte",
4874 "byte_intf",
4875 "pixel",
4876 "core",
4877 "iface",
4878 "bus";
4879
4880 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4881 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4882
4883 operating-points-v2 = <&dsi_opp_table>;
4884 power-domains = <&rpmhpd RPMHPD_MMCX>;
4885
4886 phys = <&mdss_dsi1_phy>;
4887
4888 status = "disabled";
4889
4890 #address-cells = <1>;
4891 #size-cells = <0>;
4892
4893 ports {
4894 #address-cells = <1>;
4895 #size-cells = <0>;
4896
4897 port@0 {
4898 reg = <0>;
4899 mdss_dsi1_in: endpoint {
4900 remote-endpoint = <&dpu_intf2_out>;
4901 };
4902 };
4903
4904 port@1 {
4905 reg = <1>;
4906 mdss_dsi1_out: endpoint {
4907 };
4908 };
4909 };
4910 };
4911
4912 mdss_dsi1_phy: phy@ae96400 {
4913 compatible = "qcom,dsi-phy-7nm";
4914 reg = <0 0x0ae96400 0 0x200>,
4915 <0 0x0ae96600 0 0x280>,
4916 <0 0x0ae96900 0 0x260>;
4917 reg-names = "dsi_phy",
4918 "dsi_phy_lane",
4919 "dsi_pll";
4920
4921 #clock-cells = <1>;
4922 #phy-cells = <0>;
4923
4924 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4925 <&rpmhcc RPMH_CXO_CLK>;
4926 clock-names = "iface", "ref";
4927
4928 status = "disabled";
4929 };
4930 };
4931
4932 dispcc: clock-controller@af00000 {
4933 compatible = "qcom,sm8250-dispcc";
4934 reg = <0 0x0af00000 0 0x10000>;
4935 power-domains = <&rpmhpd RPMHPD_MMCX>;
4936 required-opps = <&rpmhpd_opp_low_svs>;
4937 clocks = <&rpmhcc RPMH_CXO_CLK>,
4938 <&mdss_dsi0_phy 0>,
4939 <&mdss_dsi0_phy 1>,
4940 <&mdss_dsi1_phy 0>,
4941 <&mdss_dsi1_phy 1>,
4942 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4943 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4944 clock-names = "bi_tcxo",
4945 "dsi0_phy_pll_out_byteclk",
4946 "dsi0_phy_pll_out_dsiclk",
4947 "dsi1_phy_pll_out_byteclk",
4948 "dsi1_phy_pll_out_dsiclk",
4949 "dp_phy_pll_link_clk",
4950 "dp_phy_pll_vco_div_clk";
4951 #clock-cells = <1>;
4952 #reset-cells = <1>;
4953 #power-domain-cells = <1>;
4954 };
4955
4956 pdc: interrupt-controller@b220000 {
4957 compatible = "qcom,sm8250-pdc", "qcom,pdc";
4958 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4959 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4960 <125 63 1>, <126 716 12>;
4961 #interrupt-cells = <2>;
4962 interrupt-parent = <&intc>;
4963 interrupt-controller;
4964 };
4965
4966 tsens0: thermal-sensor@c263000 {
4967 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4968 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4969 <0 0x0c222000 0 0x1ff>; /* SROT */
4970 #qcom,sensors = <16>;
4971 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4972 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4973 interrupt-names = "uplow", "critical";
4974 #thermal-sensor-cells = <1>;
4975 };
4976
4977 tsens1: thermal-sensor@c265000 {
4978 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4979 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4980 <0 0x0c223000 0 0x1ff>; /* SROT */
4981 #qcom,sensors = <9>;
4982 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4983 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4984 interrupt-names = "uplow", "critical";
4985 #thermal-sensor-cells = <1>;
4986 };
4987
4988 aoss_qmp: power-management@c300000 {
4989 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
4990 reg = <0 0x0c300000 0 0x400>;
4991 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4992 IPCC_MPROC_SIGNAL_GLINK_QMP
4993 IRQ_TYPE_EDGE_RISING>;
4994 mboxes = <&ipcc IPCC_CLIENT_AOP
4995 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4996
4997 #clock-cells = <0>;
4998 };
4999
5000 sram@c3f0000 {
5001 compatible = "qcom,rpmh-stats";
5002 reg = <0 0x0c3f0000 0 0x400>;
5003 };
5004
5005 spmi_bus: spmi@c440000 {
5006 compatible = "qcom,spmi-pmic-arb";
5007 reg = <0x0 0x0c440000 0x0 0x0001100>,
5008 <0x0 0x0c600000 0x0 0x2000000>,
5009 <0x0 0x0e600000 0x0 0x0100000>,
5010 <0x0 0x0e700000 0x0 0x00a0000>,
5011 <0x0 0x0c40a000 0x0 0x0026000>;
5012 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5013 interrupt-names = "periph_irq";
5014 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5015 qcom,ee = <0>;
5016 qcom,channel = <0>;
5017 #address-cells = <2>;
5018 #size-cells = <0>;
5019 interrupt-controller;
5020 #interrupt-cells = <4>;
5021 };
5022
5023 tlmm: pinctrl@f100000 {
5024 compatible = "qcom,sm8250-pinctrl";
5025 reg = <0 0x0f100000 0 0x300000>,
5026 <0 0x0f500000 0 0x300000>,
5027 <0 0x0f900000 0 0x300000>;
5028 reg-names = "west", "south", "north";
5029 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5030 gpio-controller;
5031 #gpio-cells = <2>;
5032 interrupt-controller;
5033 #interrupt-cells = <2>;
5034 gpio-ranges = <&tlmm 0 0 181>;
5035 wakeup-parent = <&pdc>;
5036
5037 cam2_default: cam2-default-state {
5038 rst-pins {
5039 pins = "gpio78";
5040 function = "gpio";
5041 drive-strength = <2>;
5042 bias-disable;
5043 };
5044
5045 mclk-pins {
5046 pins = "gpio96";
5047 function = "cam_mclk";
5048 drive-strength = <16>;
5049 bias-disable;
5050 };
5051 };
5052
5053 cam2_suspend: cam2-suspend-state {
5054 rst-pins {
5055 pins = "gpio78";
5056 function = "gpio";
5057 drive-strength = <2>;
5058 bias-pull-down;
5059 output-low;
5060 };
5061
5062 mclk-pins {
5063 pins = "gpio96";
5064 function = "cam_mclk";
5065 drive-strength = <2>;
5066 bias-disable;
5067 };
5068 };
5069
5070 cci0_default: cci0-default-state {
5071 cci0_i2c0_default: cci0-i2c0-default-pins {
5072 /* SDA, SCL */
5073 pins = "gpio101", "gpio102";
5074 function = "cci_i2c";
5075
5076 bias-pull-up;
5077 drive-strength = <2>; /* 2 mA */
5078 };
5079
5080 cci0_i2c1_default: cci0-i2c1-default-pins {
5081 /* SDA, SCL */
5082 pins = "gpio103", "gpio104";
5083 function = "cci_i2c";
5084
5085 bias-pull-up;
5086 drive-strength = <2>; /* 2 mA */
5087 };
5088 };
5089
5090 cci0_sleep: cci0-sleep-state {
5091 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5092 /* SDA, SCL */
5093 pins = "gpio101", "gpio102";
5094 function = "cci_i2c";
5095
5096 drive-strength = <2>; /* 2 mA */
5097 bias-pull-down;
5098 };
5099
5100 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5101 /* SDA, SCL */
5102 pins = "gpio103", "gpio104";
5103 function = "cci_i2c";
5104
5105 drive-strength = <2>; /* 2 mA */
5106 bias-pull-down;
5107 };
5108 };
5109
5110 cci1_default: cci1-default-state {
5111 cci1_i2c0_default: cci1-i2c0-default-pins {
5112 /* SDA, SCL */
5113 pins = "gpio105","gpio106";
5114 function = "cci_i2c";
5115
5116 bias-pull-up;
5117 drive-strength = <2>; /* 2 mA */
5118 };
5119
5120 cci1_i2c1_default: cci1-i2c1-default-pins {
5121 /* SDA, SCL */
5122 pins = "gpio107","gpio108";
5123 function = "cci_i2c";
5124
5125 bias-pull-up;
5126 drive-strength = <2>; /* 2 mA */
5127 };
5128 };
5129
5130 cci1_sleep: cci1-sleep-state {
5131 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5132 /* SDA, SCL */
5133 pins = "gpio105","gpio106";
5134 function = "cci_i2c";
5135
5136 bias-pull-down;
5137 drive-strength = <2>; /* 2 mA */
5138 };
5139
5140 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5141 /* SDA, SCL */
5142 pins = "gpio107","gpio108";
5143 function = "cci_i2c";
5144
5145 bias-pull-down;
5146 drive-strength = <2>; /* 2 mA */
5147 };
5148 };
5149
5150 pri_mi2s_active: pri-mi2s-active-state {
5151 sclk-pins {
5152 pins = "gpio138";
5153 function = "mi2s0_sck";
5154 drive-strength = <8>;
5155 bias-disable;
5156 };
5157
5158 ws-pins {
5159 pins = "gpio141";
5160 function = "mi2s0_ws";
5161 drive-strength = <8>;
5162 output-high;
5163 };
5164
5165 data0-pins {
5166 pins = "gpio139";
5167 function = "mi2s0_data0";
5168 drive-strength = <8>;
5169 bias-disable;
5170 output-high;
5171 };
5172
5173 data1-pins {
5174 pins = "gpio140";
5175 function = "mi2s0_data1";
5176 drive-strength = <8>;
5177 output-high;
5178 };
5179 };
5180
5181 qup_i2c0_default: qup-i2c0-default-state {
5182 pins = "gpio28", "gpio29";
5183 function = "qup0";
5184 drive-strength = <2>;
5185 bias-disable;
5186 };
5187
5188 qup_i2c1_default: qup-i2c1-default-state {
5189 pins = "gpio4", "gpio5";
5190 function = "qup1";
5191 drive-strength = <2>;
5192 bias-disable;
5193 };
5194
5195 qup_i2c2_default: qup-i2c2-default-state {
5196 pins = "gpio115", "gpio116";
5197 function = "qup2";
5198 drive-strength = <2>;
5199 bias-disable;
5200 };
5201
5202 qup_i2c3_default: qup-i2c3-default-state {
5203 pins = "gpio119", "gpio120";
5204 function = "qup3";
5205 drive-strength = <2>;
5206 bias-disable;
5207 };
5208
5209 qup_i2c4_default: qup-i2c4-default-state {
5210 pins = "gpio8", "gpio9";
5211 function = "qup4";
5212 drive-strength = <2>;
5213 bias-disable;
5214 };
5215
5216 qup_i2c5_default: qup-i2c5-default-state {
5217 pins = "gpio12", "gpio13";
5218 function = "qup5";
5219 drive-strength = <2>;
5220 bias-disable;
5221 };
5222
5223 qup_i2c6_default: qup-i2c6-default-state {
5224 pins = "gpio16", "gpio17";
5225 function = "qup6";
5226 drive-strength = <2>;
5227 bias-disable;
5228 };
5229
5230 qup_i2c7_default: qup-i2c7-default-state {
5231 pins = "gpio20", "gpio21";
5232 function = "qup7";
5233 drive-strength = <2>;
5234 bias-disable;
5235 };
5236
5237 qup_i2c8_default: qup-i2c8-default-state {
5238 pins = "gpio24", "gpio25";
5239 function = "qup8";
5240 drive-strength = <2>;
5241 bias-disable;
5242 };
5243
5244 qup_i2c9_default: qup-i2c9-default-state {
5245 pins = "gpio125", "gpio126";
5246 function = "qup9";
5247 drive-strength = <2>;
5248 bias-disable;
5249 };
5250
5251 qup_i2c10_default: qup-i2c10-default-state {
5252 pins = "gpio129", "gpio130";
5253 function = "qup10";
5254 drive-strength = <2>;
5255 bias-disable;
5256 };
5257
5258 qup_i2c11_default: qup-i2c11-default-state {
5259 pins = "gpio60", "gpio61";
5260 function = "qup11";
5261 drive-strength = <2>;
5262 bias-disable;
5263 };
5264
5265 qup_i2c12_default: qup-i2c12-default-state {
5266 pins = "gpio32", "gpio33";
5267 function = "qup12";
5268 drive-strength = <2>;
5269 bias-disable;
5270 };
5271
5272 qup_i2c13_default: qup-i2c13-default-state {
5273 pins = "gpio36", "gpio37";
5274 function = "qup13";
5275 drive-strength = <2>;
5276 bias-disable;
5277 };
5278
5279 qup_i2c14_default: qup-i2c14-default-state {
5280 pins = "gpio40", "gpio41";
5281 function = "qup14";
5282 drive-strength = <2>;
5283 bias-disable;
5284 };
5285
5286 qup_i2c15_default: qup-i2c15-default-state {
5287 pins = "gpio44", "gpio45";
5288 function = "qup15";
5289 drive-strength = <2>;
5290 bias-disable;
5291 };
5292
5293 qup_i2c16_default: qup-i2c16-default-state {
5294 pins = "gpio48", "gpio49";
5295 function = "qup16";
5296 drive-strength = <2>;
5297 bias-disable;
5298 };
5299
5300 qup_i2c17_default: qup-i2c17-default-state {
5301 pins = "gpio52", "gpio53";
5302 function = "qup17";
5303 drive-strength = <2>;
5304 bias-disable;
5305 };
5306
5307 qup_i2c18_default: qup-i2c18-default-state {
5308 pins = "gpio56", "gpio57";
5309 function = "qup18";
5310 drive-strength = <2>;
5311 bias-disable;
5312 };
5313
5314 qup_i2c19_default: qup-i2c19-default-state {
5315 pins = "gpio0", "gpio1";
5316 function = "qup19";
5317 drive-strength = <2>;
5318 bias-disable;
5319 };
5320
5321 qup_spi0_cs: qup-spi0-cs-state {
5322 pins = "gpio31";
5323 function = "qup0";
5324 };
5325
5326 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5327 pins = "gpio31";
5328 function = "gpio";
5329 };
5330
5331 qup_spi0_data_clk: qup-spi0-data-clk-state {
5332 pins = "gpio28", "gpio29",
5333 "gpio30";
5334 function = "qup0";
5335 };
5336
5337 qup_spi1_cs: qup-spi1-cs-state {
5338 pins = "gpio7";
5339 function = "qup1";
5340 };
5341
5342 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5343 pins = "gpio7";
5344 function = "gpio";
5345 };
5346
5347 qup_spi1_data_clk: qup-spi1-data-clk-state {
5348 pins = "gpio4", "gpio5",
5349 "gpio6";
5350 function = "qup1";
5351 };
5352
5353 qup_spi2_cs: qup-spi2-cs-state {
5354 pins = "gpio118";
5355 function = "qup2";
5356 };
5357
5358 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5359 pins = "gpio118";
5360 function = "gpio";
5361 };
5362
5363 qup_spi2_data_clk: qup-spi2-data-clk-state {
5364 pins = "gpio115", "gpio116",
5365 "gpio117";
5366 function = "qup2";
5367 };
5368
5369 qup_spi3_cs: qup-spi3-cs-state {
5370 pins = "gpio122";
5371 function = "qup3";
5372 };
5373
5374 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5375 pins = "gpio122";
5376 function = "gpio";
5377 };
5378
5379 qup_spi3_data_clk: qup-spi3-data-clk-state {
5380 pins = "gpio119", "gpio120",
5381 "gpio121";
5382 function = "qup3";
5383 };
5384
5385 qup_spi4_cs: qup-spi4-cs-state {
5386 pins = "gpio11";
5387 function = "qup4";
5388 };
5389
5390 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5391 pins = "gpio11";
5392 function = "gpio";
5393 };
5394
5395 qup_spi4_data_clk: qup-spi4-data-clk-state {
5396 pins = "gpio8", "gpio9",
5397 "gpio10";
5398 function = "qup4";
5399 };
5400
5401 qup_spi5_cs: qup-spi5-cs-state {
5402 pins = "gpio15";
5403 function = "qup5";
5404 };
5405
5406 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5407 pins = "gpio15";
5408 function = "gpio";
5409 };
5410
5411 qup_spi5_data_clk: qup-spi5-data-clk-state {
5412 pins = "gpio12", "gpio13",
5413 "gpio14";
5414 function = "qup5";
5415 };
5416
5417 qup_spi6_cs: qup-spi6-cs-state {
5418 pins = "gpio19";
5419 function = "qup6";
5420 };
5421
5422 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5423 pins = "gpio19";
5424 function = "gpio";
5425 };
5426
5427 qup_spi6_data_clk: qup-spi6-data-clk-state {
5428 pins = "gpio16", "gpio17",
5429 "gpio18";
5430 function = "qup6";
5431 };
5432
5433 qup_spi7_cs: qup-spi7-cs-state {
5434 pins = "gpio23";
5435 function = "qup7";
5436 };
5437
5438 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5439 pins = "gpio23";
5440 function = "gpio";
5441 };
5442
5443 qup_spi7_data_clk: qup-spi7-data-clk-state {
5444 pins = "gpio20", "gpio21",
5445 "gpio22";
5446 function = "qup7";
5447 };
5448
5449 qup_spi8_cs: qup-spi8-cs-state {
5450 pins = "gpio27";
5451 function = "qup8";
5452 };
5453
5454 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5455 pins = "gpio27";
5456 function = "gpio";
5457 };
5458
5459 qup_spi8_data_clk: qup-spi8-data-clk-state {
5460 pins = "gpio24", "gpio25",
5461 "gpio26";
5462 function = "qup8";
5463 };
5464
5465 qup_spi9_cs: qup-spi9-cs-state {
5466 pins = "gpio128";
5467 function = "qup9";
5468 };
5469
5470 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5471 pins = "gpio128";
5472 function = "gpio";
5473 };
5474
5475 qup_spi9_data_clk: qup-spi9-data-clk-state {
5476 pins = "gpio125", "gpio126",
5477 "gpio127";
5478 function = "qup9";
5479 };
5480
5481 qup_spi10_cs: qup-spi10-cs-state {
5482 pins = "gpio132";
5483 function = "qup10";
5484 };
5485
5486 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5487 pins = "gpio132";
5488 function = "gpio";
5489 };
5490
5491 qup_spi10_data_clk: qup-spi10-data-clk-state {
5492 pins = "gpio129", "gpio130",
5493 "gpio131";
5494 function = "qup10";
5495 };
5496
5497 qup_spi11_cs: qup-spi11-cs-state {
5498 pins = "gpio63";
5499 function = "qup11";
5500 };
5501
5502 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5503 pins = "gpio63";
5504 function = "gpio";
5505 };
5506
5507 qup_spi11_data_clk: qup-spi11-data-clk-state {
5508 pins = "gpio60", "gpio61",
5509 "gpio62";
5510 function = "qup11";
5511 };
5512
5513 qup_spi12_cs: qup-spi12-cs-state {
5514 pins = "gpio35";
5515 function = "qup12";
5516 };
5517
5518 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5519 pins = "gpio35";
5520 function = "gpio";
5521 };
5522
5523 qup_spi12_data_clk: qup-spi12-data-clk-state {
5524 pins = "gpio32", "gpio33",
5525 "gpio34";
5526 function = "qup12";
5527 };
5528
5529 qup_spi13_cs: qup-spi13-cs-state {
5530 pins = "gpio39";
5531 function = "qup13";
5532 };
5533
5534 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5535 pins = "gpio39";
5536 function = "gpio";
5537 };
5538
5539 qup_spi13_data_clk: qup-spi13-data-clk-state {
5540 pins = "gpio36", "gpio37",
5541 "gpio38";
5542 function = "qup13";
5543 };
5544
5545 qup_spi14_cs: qup-spi14-cs-state {
5546 pins = "gpio43";
5547 function = "qup14";
5548 };
5549
5550 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5551 pins = "gpio43";
5552 function = "gpio";
5553 };
5554
5555 qup_spi14_data_clk: qup-spi14-data-clk-state {
5556 pins = "gpio40", "gpio41",
5557 "gpio42";
5558 function = "qup14";
5559 };
5560
5561 qup_spi15_cs: qup-spi15-cs-state {
5562 pins = "gpio47";
5563 function = "qup15";
5564 };
5565
5566 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5567 pins = "gpio47";
5568 function = "gpio";
5569 };
5570
5571 qup_spi15_data_clk: qup-spi15-data-clk-state {
5572 pins = "gpio44", "gpio45",
5573 "gpio46";
5574 function = "qup15";
5575 };
5576
5577 qup_spi16_cs: qup-spi16-cs-state {
5578 pins = "gpio51";
5579 function = "qup16";
5580 };
5581
5582 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5583 pins = "gpio51";
5584 function = "gpio";
5585 };
5586
5587 qup_spi16_data_clk: qup-spi16-data-clk-state {
5588 pins = "gpio48", "gpio49",
5589 "gpio50";
5590 function = "qup16";
5591 };
5592
5593 qup_spi17_cs: qup-spi17-cs-state {
5594 pins = "gpio55";
5595 function = "qup17";
5596 };
5597
5598 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5599 pins = "gpio55";
5600 function = "gpio";
5601 };
5602
5603 qup_spi17_data_clk: qup-spi17-data-clk-state {
5604 pins = "gpio52", "gpio53",
5605 "gpio54";
5606 function = "qup17";
5607 };
5608
5609 qup_spi18_cs: qup-spi18-cs-state {
5610 pins = "gpio59";
5611 function = "qup18";
5612 };
5613
5614 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5615 pins = "gpio59";
5616 function = "gpio";
5617 };
5618
5619 qup_spi18_data_clk: qup-spi18-data-clk-state {
5620 pins = "gpio56", "gpio57",
5621 "gpio58";
5622 function = "qup18";
5623 };
5624
5625 qup_spi19_cs: qup-spi19-cs-state {
5626 pins = "gpio3";
5627 function = "qup19";
5628 };
5629
5630 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5631 pins = "gpio3";
5632 function = "gpio";
5633 };
5634
5635 qup_spi19_data_clk: qup-spi19-data-clk-state {
5636 pins = "gpio0", "gpio1",
5637 "gpio2";
5638 function = "qup19";
5639 };
5640
5641 qup_uart2_default: qup-uart2-default-state {
5642 pins = "gpio117", "gpio118";
5643 function = "qup2";
5644 };
5645
5646 qup_uart6_default: qup-uart6-default-state {
5647 pins = "gpio16", "gpio17", "gpio18", "gpio19";
5648 function = "qup6";
5649 };
5650
5651 qup_uart12_default: qup-uart12-default-state {
5652 pins = "gpio34", "gpio35";
5653 function = "qup12";
5654 };
5655
5656 qup_uart17_default: qup-uart17-default-state {
5657 pins = "gpio52", "gpio53", "gpio54", "gpio55";
5658 function = "qup17";
5659 };
5660
5661 qup_uart18_default: qup-uart18-default-state {
5662 pins = "gpio58", "gpio59";
5663 function = "qup18";
5664 };
5665
5666 tert_mi2s_active: tert-mi2s-active-state {
5667 sck-pins {
5668 pins = "gpio133";
5669 function = "mi2s2_sck";
5670 drive-strength = <8>;
5671 bias-disable;
5672 };
5673
5674 data0-pins {
5675 pins = "gpio134";
5676 function = "mi2s2_data0";
5677 drive-strength = <8>;
5678 bias-disable;
5679 output-high;
5680 };
5681
5682 ws-pins {
5683 pins = "gpio135";
5684 function = "mi2s2_ws";
5685 drive-strength = <8>;
5686 output-high;
5687 };
5688 };
5689
5690 sdc2_sleep_state: sdc2-sleep-state {
5691 clk-pins {
5692 pins = "sdc2_clk";
5693 drive-strength = <2>;
5694 bias-disable;
5695 };
5696
5697 cmd-pins {
5698 pins = "sdc2_cmd";
5699 drive-strength = <2>;
5700 bias-pull-up;
5701 };
5702
5703 data-pins {
5704 pins = "sdc2_data";
5705 drive-strength = <2>;
5706 bias-pull-up;
5707 };
5708 };
5709
5710 pcie0_default_state: pcie0-default-state {
5711 perst-pins {
5712 pins = "gpio79";
5713 function = "gpio";
5714 drive-strength = <2>;
5715 bias-pull-down;
5716 };
5717
5718 clkreq-pins {
5719 pins = "gpio80";
5720 function = "pci_e0";
5721 drive-strength = <2>;
5722 bias-pull-up;
5723 };
5724
5725 wake-pins {
5726 pins = "gpio81";
5727 function = "gpio";
5728 drive-strength = <2>;
5729 bias-pull-up;
5730 };
5731 };
5732
5733 pcie1_default_state: pcie1-default-state {
5734 perst-pins {
5735 pins = "gpio82";
5736 function = "gpio";
5737 drive-strength = <2>;
5738 bias-pull-down;
5739 };
5740
5741 clkreq-pins {
5742 pins = "gpio83";
5743 function = "pci_e1";
5744 drive-strength = <2>;
5745 bias-pull-up;
5746 };
5747
5748 wake-pins {
5749 pins = "gpio84";
5750 function = "gpio";
5751 drive-strength = <2>;
5752 bias-pull-up;
5753 };
5754 };
5755
5756 pcie2_default_state: pcie2-default-state {
5757 perst-pins {
5758 pins = "gpio85";
5759 function = "gpio";
5760 drive-strength = <2>;
5761 bias-pull-down;
5762 };
5763
5764 clkreq-pins {
5765 pins = "gpio86";
5766 function = "pci_e2";
5767 drive-strength = <2>;
5768 bias-pull-up;
5769 };
5770
5771 wake-pins {
5772 pins = "gpio87";
5773 function = "gpio";
5774 drive-strength = <2>;
5775 bias-pull-up;
5776 };
5777 };
5778 };
5779
5780 apps_smmu: iommu@15000000 {
5781 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5782 reg = <0 0x15000000 0 0x100000>;
5783 #iommu-cells = <2>;
5784 #global-interrupts = <2>;
5785 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5786 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5787 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5788 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5789 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5790 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5791 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5792 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5793 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5794 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5795 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5796 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5797 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5798 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5799 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5800 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5801 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5802 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5803 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5804 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5805 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5806 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5807 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5808 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5809 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5810 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5811 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5812 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5813 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5814 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5815 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5816 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5817 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5818 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5819 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5820 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5821 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5822 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5823 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5824 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5825 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5826 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5827 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5828 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5829 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5830 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5831 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5832 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5833 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5834 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5835 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5836 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5837 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5838 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5839 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5840 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5841 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5842 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5843 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5844 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5845 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5846 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5847 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5848 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5849 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5850 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5851 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5852 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5853 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5854 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5855 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5856 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5857 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5883 dma-coherent;
5884 };
5885
5886 adsp: remoteproc@17300000 {
5887 compatible = "qcom,sm8250-adsp-pas";
5888 reg = <0 0x17300000 0 0x100>;
5889
5890 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5891 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5892 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5893 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5894 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5895 interrupt-names = "wdog", "fatal", "ready",
5896 "handover", "stop-ack";
5897
5898 clocks = <&rpmhcc RPMH_CXO_CLK>;
5899 clock-names = "xo";
5900
5901 power-domains = <&rpmhpd RPMHPD_LCX>,
5902 <&rpmhpd RPMHPD_LMX>;
5903 power-domain-names = "lcx", "lmx";
5904
5905 memory-region = <&adsp_mem>;
5906
5907 qcom,qmp = <&aoss_qmp>;
5908
5909 qcom,smem-states = <&smp2p_adsp_out 0>;
5910 qcom,smem-state-names = "stop";
5911
5912 status = "disabled";
5913
5914 glink-edge {
5915 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5916 IPCC_MPROC_SIGNAL_GLINK_QMP
5917 IRQ_TYPE_EDGE_RISING>;
5918 mboxes = <&ipcc IPCC_CLIENT_LPASS
5919 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5920
5921 label = "lpass";
5922 qcom,remote-pid = <2>;
5923
5924 apr {
5925 compatible = "qcom,apr-v2";
5926 qcom,glink-channels = "apr_audio_svc";
5927 qcom,domain = <APR_DOMAIN_ADSP>;
5928 #address-cells = <1>;
5929 #size-cells = <0>;
5930
5931 service@3 {
5932 reg = <APR_SVC_ADSP_CORE>;
5933 compatible = "qcom,q6core";
5934 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5935 };
5936
5937 q6afe: service@4 {
5938 compatible = "qcom,q6afe";
5939 reg = <APR_SVC_AFE>;
5940 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5941 q6afedai: dais {
5942 compatible = "qcom,q6afe-dais";
5943 #address-cells = <1>;
5944 #size-cells = <0>;
5945 #sound-dai-cells = <1>;
5946 };
5947
5948 q6afecc: clock-controller {
5949 compatible = "qcom,q6afe-clocks";
5950 #clock-cells = <2>;
5951 };
5952 };
5953
5954 q6asm: service@7 {
5955 compatible = "qcom,q6asm";
5956 reg = <APR_SVC_ASM>;
5957 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5958 q6asmdai: dais {
5959 compatible = "qcom,q6asm-dais";
5960 #address-cells = <1>;
5961 #size-cells = <0>;
5962 #sound-dai-cells = <1>;
5963 iommus = <&apps_smmu 0x1801 0x0>;
5964 };
5965 };
5966
5967 q6adm: service@8 {
5968 compatible = "qcom,q6adm";
5969 reg = <APR_SVC_ADM>;
5970 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5971 q6routing: routing {
5972 compatible = "qcom,q6adm-routing";
5973 #sound-dai-cells = <0>;
5974 };
5975 };
5976 };
5977
5978 fastrpc {
5979 compatible = "qcom,fastrpc";
5980 qcom,glink-channels = "fastrpcglink-apps-dsp";
5981 label = "adsp";
5982 qcom,non-secure-domain;
5983 #address-cells = <1>;
5984 #size-cells = <0>;
5985
5986 compute-cb@3 {
5987 compatible = "qcom,fastrpc-compute-cb";
5988 reg = <3>;
5989 iommus = <&apps_smmu 0x1803 0x0>;
5990 };
5991
5992 compute-cb@4 {
5993 compatible = "qcom,fastrpc-compute-cb";
5994 reg = <4>;
5995 iommus = <&apps_smmu 0x1804 0x0>;
5996 };
5997
5998 compute-cb@5 {
5999 compatible = "qcom,fastrpc-compute-cb";
6000 reg = <5>;
6001 iommus = <&apps_smmu 0x1805 0x0>;
6002 };
6003 };
6004 };
6005 };
6006
6007 intc: interrupt-controller@17a00000 {
6008 compatible = "arm,gic-v3";
6009 #interrupt-cells = <3>;
6010 interrupt-controller;
6011 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6012 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6013 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6014 };
6015
6016 watchdog@17c10000 {
6017 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6018 reg = <0 0x17c10000 0 0x1000>;
6019 clocks = <&sleep_clk>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]6020 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]6021 };
6022
6023 timer@17c20000 {
6024 #address-cells = <1>;
6025 #size-cells = <1>;
6026 ranges = <0 0 0 0x20000000>;
6027 compatible = "arm,armv7-timer-mem";
6028 reg = <0x0 0x17c20000 0x0 0x1000>;
6029 clock-frequency = <19200000>;
6030
6031 frame@17c21000 {
6032 frame-number = <0>;
6033 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6034 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6035 reg = <0x17c21000 0x1000>,
6036 <0x17c22000 0x1000>;
6037 };
6038
6039 frame@17c23000 {
6040 frame-number = <1>;
6041 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6042 reg = <0x17c23000 0x1000>;
6043 status = "disabled";
6044 };
6045
6046 frame@17c25000 {
6047 frame-number = <2>;
6048 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6049 reg = <0x17c25000 0x1000>;
6050 status = "disabled";
6051 };
6052
6053 frame@17c27000 {
6054 frame-number = <3>;
6055 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6056 reg = <0x17c27000 0x1000>;
6057 status = "disabled";
6058 };
6059
6060 frame@17c29000 {
6061 frame-number = <4>;
6062 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6063 reg = <0x17c29000 0x1000>;
6064 status = "disabled";
6065 };
6066
6067 frame@17c2b000 {
6068 frame-number = <5>;
6069 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6070 reg = <0x17c2b000 0x1000>;
6071 status = "disabled";
6072 };
6073
6074 frame@17c2d000 {
6075 frame-number = <6>;
6076 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6077 reg = <0x17c2d000 0x1000>;
6078 status = "disabled";
6079 };
6080 };
6081
6082 apps_rsc: rsc@18200000 {
6083 label = "apps_rsc";
6084 compatible = "qcom,rpmh-rsc";
6085 reg = <0x0 0x18200000 0x0 0x10000>,
6086 <0x0 0x18210000 0x0 0x10000>,
6087 <0x0 0x18220000 0x0 0x10000>;
6088 reg-names = "drv-0", "drv-1", "drv-2";
6089 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6090 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6091 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6092 qcom,tcs-offset = <0xd00>;
6093 qcom,drv-id = <2>;
6094 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6095 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6096 power-domains = <&CLUSTER_PD>;
6097
6098 rpmhcc: clock-controller {
6099 compatible = "qcom,sm8250-rpmh-clk";
6100 #clock-cells = <1>;
6101 clock-names = "xo";
6102 clocks = <&xo_board>;
6103 };
6104
6105 rpmhpd: power-controller {
6106 compatible = "qcom,sm8250-rpmhpd";
6107 #power-domain-cells = <1>;
6108 operating-points-v2 = <&rpmhpd_opp_table>;
6109
6110 rpmhpd_opp_table: opp-table {
6111 compatible = "operating-points-v2";
6112
6113 rpmhpd_opp_ret: opp1 {
6114 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6115 };
6116
6117 rpmhpd_opp_min_svs: opp2 {
6118 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6119 };
6120
6121 rpmhpd_opp_low_svs: opp3 {
6122 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6123 };
6124
6125 rpmhpd_opp_svs: opp4 {
6126 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6127 };
6128
6129 rpmhpd_opp_svs_l1: opp5 {
6130 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6131 };
6132
6133 rpmhpd_opp_nom: opp6 {
6134 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6135 };
6136
6137 rpmhpd_opp_nom_l1: opp7 {
6138 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6139 };
6140
6141 rpmhpd_opp_nom_l2: opp8 {
6142 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6143 };
6144
6145 rpmhpd_opp_turbo: opp9 {
6146 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6147 };
6148
6149 rpmhpd_opp_turbo_l1: opp10 {
6150 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6151 };
6152 };
6153 };
6154
6155 apps_bcm_voter: bcm-voter {
6156 compatible = "qcom,bcm-voter";
6157 };
6158 };
6159
6160 epss_l3: interconnect@18590000 {
6161 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6162 reg = <0 0x18590000 0 0x1000>;
6163
6164 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6165 clock-names = "xo", "alternate";
6166
6167 #interconnect-cells = <1>;
6168 };
6169
6170 cpufreq_hw: cpufreq@18591000 {
6171 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6172 reg = <0 0x18591000 0 0x1000>,
6173 <0 0x18592000 0 0x1000>,
6174 <0 0x18593000 0 0x1000>;
6175 reg-names = "freq-domain0", "freq-domain1",
6176 "freq-domain2";
6177
6178 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6179 clock-names = "xo", "alternate";
6180 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6181 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6182 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6183 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6184 #freq-domain-cells = <1>;
6185 #clock-cells = <1>;
6186 };
6187 };
6188
6189 sound: sound {
6190 };
6191
6192 timer {
6193 compatible = "arm,armv8-timer";
6194 interrupts = <GIC_PPI 13
6195 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6196 <GIC_PPI 14
6197 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6198 <GIC_PPI 11
6199 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6200 <GIC_PPI 10
6201 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6202 };
6203
6204 thermal-zones {
6205 cpu0-thermal {
6206 polling-delay-passive = <250>;
6207 polling-delay = <1000>;
6208
6209 thermal-sensors = <&tsens0 1>;
6210
6211 trips {
6212 cpu0_alert0: trip-point0 {
6213 temperature = <90000>;
6214 hysteresis = <2000>;
6215 type = "passive";
6216 };
6217
6218 cpu0_alert1: trip-point1 {
6219 temperature = <95000>;
6220 hysteresis = <2000>;
6221 type = "passive";
6222 };
6223
6224 cpu0_crit: cpu-crit {
6225 temperature = <110000>;
6226 hysteresis = <1000>;
6227 type = "critical";
6228 };
6229 };
6230
6231 cooling-maps {
6232 map0 {
6233 trip = <&cpu0_alert0>;
6234 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6235 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6236 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6237 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6238 };
6239 map1 {
6240 trip = <&cpu0_alert1>;
6241 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6242 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6243 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6244 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6245 };
6246 };
6247 };
6248
6249 cpu1-thermal {
6250 polling-delay-passive = <250>;
6251 polling-delay = <1000>;
6252
6253 thermal-sensors = <&tsens0 2>;
6254
6255 trips {
6256 cpu1_alert0: trip-point0 {
6257 temperature = <90000>;
6258 hysteresis = <2000>;
6259 type = "passive";
6260 };
6261
6262 cpu1_alert1: trip-point1 {
6263 temperature = <95000>;
6264 hysteresis = <2000>;
6265 type = "passive";
6266 };
6267
6268 cpu1_crit: cpu-crit {
6269 temperature = <110000>;
6270 hysteresis = <1000>;
6271 type = "critical";
6272 };
6273 };
6274
6275 cooling-maps {
6276 map0 {
6277 trip = <&cpu1_alert0>;
6278 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6279 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6280 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6281 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6282 };
6283 map1 {
6284 trip = <&cpu1_alert1>;
6285 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6286 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6287 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6288 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6289 };
6290 };
6291 };
6292
6293 cpu2-thermal {
6294 polling-delay-passive = <250>;
6295 polling-delay = <1000>;
6296
6297 thermal-sensors = <&tsens0 3>;
6298
6299 trips {
6300 cpu2_alert0: trip-point0 {
6301 temperature = <90000>;
6302 hysteresis = <2000>;
6303 type = "passive";
6304 };
6305
6306 cpu2_alert1: trip-point1 {
6307 temperature = <95000>;
6308 hysteresis = <2000>;
6309 type = "passive";
6310 };
6311
6312 cpu2_crit: cpu-crit {
6313 temperature = <110000>;
6314 hysteresis = <1000>;
6315 type = "critical";
6316 };
6317 };
6318
6319 cooling-maps {
6320 map0 {
6321 trip = <&cpu2_alert0>;
6322 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6323 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6324 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6325 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6326 };
6327 map1 {
6328 trip = <&cpu2_alert1>;
6329 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6330 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6331 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6332 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6333 };
6334 };
6335 };
6336
6337 cpu3-thermal {
6338 polling-delay-passive = <250>;
6339 polling-delay = <1000>;
6340
6341 thermal-sensors = <&tsens0 4>;
6342
6343 trips {
6344 cpu3_alert0: trip-point0 {
6345 temperature = <90000>;
6346 hysteresis = <2000>;
6347 type = "passive";
6348 };
6349
6350 cpu3_alert1: trip-point1 {
6351 temperature = <95000>;
6352 hysteresis = <2000>;
6353 type = "passive";
6354 };
6355
6356 cpu3_crit: cpu-crit {
6357 temperature = <110000>;
6358 hysteresis = <1000>;
6359 type = "critical";
6360 };
6361 };
6362
6363 cooling-maps {
6364 map0 {
6365 trip = <&cpu3_alert0>;
6366 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6367 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6368 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6369 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6370 };
6371 map1 {
6372 trip = <&cpu3_alert1>;
6373 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6374 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6375 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6376 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6377 };
6378 };
6379 };
6380
6381 cpu4-top-thermal {
6382 polling-delay-passive = <250>;
6383 polling-delay = <1000>;
6384
6385 thermal-sensors = <&tsens0 7>;
6386
6387 trips {
6388 cpu4_top_alert0: trip-point0 {
6389 temperature = <90000>;
6390 hysteresis = <2000>;
6391 type = "passive";
6392 };
6393
6394 cpu4_top_alert1: trip-point1 {
6395 temperature = <95000>;
6396 hysteresis = <2000>;
6397 type = "passive";
6398 };
6399
6400 cpu4_top_crit: cpu-crit {
6401 temperature = <110000>;
6402 hysteresis = <1000>;
6403 type = "critical";
6404 };
6405 };
6406
6407 cooling-maps {
6408 map0 {
6409 trip = <&cpu4_top_alert0>;
6410 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6411 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6412 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6413 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6414 };
6415 map1 {
6416 trip = <&cpu4_top_alert1>;
6417 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6418 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6419 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6420 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6421 };
6422 };
6423 };
6424
6425 cpu5-top-thermal {
6426 polling-delay-passive = <250>;
6427 polling-delay = <1000>;
6428
6429 thermal-sensors = <&tsens0 8>;
6430
6431 trips {
6432 cpu5_top_alert0: trip-point0 {
6433 temperature = <90000>;
6434 hysteresis = <2000>;
6435 type = "passive";
6436 };
6437
6438 cpu5_top_alert1: trip-point1 {
6439 temperature = <95000>;
6440 hysteresis = <2000>;
6441 type = "passive";
6442 };
6443
6444 cpu5_top_crit: cpu-crit {
6445 temperature = <110000>;
6446 hysteresis = <1000>;
6447 type = "critical";
6448 };
6449 };
6450
6451 cooling-maps {
6452 map0 {
6453 trip = <&cpu5_top_alert0>;
6454 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6455 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6456 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6457 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6458 };
6459 map1 {
6460 trip = <&cpu5_top_alert1>;
6461 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6462 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6463 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6464 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6465 };
6466 };
6467 };
6468
6469 cpu6-top-thermal {
6470 polling-delay-passive = <250>;
6471 polling-delay = <1000>;
6472
6473 thermal-sensors = <&tsens0 9>;
6474
6475 trips {
6476 cpu6_top_alert0: trip-point0 {
6477 temperature = <90000>;
6478 hysteresis = <2000>;
6479 type = "passive";
6480 };
6481
6482 cpu6_top_alert1: trip-point1 {
6483 temperature = <95000>;
6484 hysteresis = <2000>;
6485 type = "passive";
6486 };
6487
6488 cpu6_top_crit: cpu-crit {
6489 temperature = <110000>;
6490 hysteresis = <1000>;
6491 type = "critical";
6492 };
6493 };
6494
6495 cooling-maps {
6496 map0 {
6497 trip = <&cpu6_top_alert0>;
6498 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6499 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6500 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6501 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6502 };
6503 map1 {
6504 trip = <&cpu6_top_alert1>;
6505 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6506 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6507 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6508 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6509 };
6510 };
6511 };
6512
6513 cpu7-top-thermal {
6514 polling-delay-passive = <250>;
6515 polling-delay = <1000>;
6516
6517 thermal-sensors = <&tsens0 10>;
6518
6519 trips {
6520 cpu7_top_alert0: trip-point0 {
6521 temperature = <90000>;
6522 hysteresis = <2000>;
6523 type = "passive";
6524 };
6525
6526 cpu7_top_alert1: trip-point1 {
6527 temperature = <95000>;
6528 hysteresis = <2000>;
6529 type = "passive";
6530 };
6531
6532 cpu7_top_crit: cpu-crit {
6533 temperature = <110000>;
6534 hysteresis = <1000>;
6535 type = "critical";
6536 };
6537 };
6538
6539 cooling-maps {
6540 map0 {
6541 trip = <&cpu7_top_alert0>;
6542 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6543 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6544 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6545 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6546 };
6547 map1 {
6548 trip = <&cpu7_top_alert1>;
6549 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6550 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6551 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6552 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6553 };
6554 };
6555 };
6556
6557 cpu4-bottom-thermal {
6558 polling-delay-passive = <250>;
6559 polling-delay = <1000>;
6560
6561 thermal-sensors = <&tsens0 11>;
6562
6563 trips {
6564 cpu4_bottom_alert0: trip-point0 {
6565 temperature = <90000>;
6566 hysteresis = <2000>;
6567 type = "passive";
6568 };
6569
6570 cpu4_bottom_alert1: trip-point1 {
6571 temperature = <95000>;
6572 hysteresis = <2000>;
6573 type = "passive";
6574 };
6575
6576 cpu4_bottom_crit: cpu-crit {
6577 temperature = <110000>;
6578 hysteresis = <1000>;
6579 type = "critical";
6580 };
6581 };
6582
6583 cooling-maps {
6584 map0 {
6585 trip = <&cpu4_bottom_alert0>;
6586 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6587 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6588 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6589 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6590 };
6591 map1 {
6592 trip = <&cpu4_bottom_alert1>;
6593 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6594 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6595 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6596 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6597 };
6598 };
6599 };
6600
6601 cpu5-bottom-thermal {
6602 polling-delay-passive = <250>;
6603 polling-delay = <1000>;
6604
6605 thermal-sensors = <&tsens0 12>;
6606
6607 trips {
6608 cpu5_bottom_alert0: trip-point0 {
6609 temperature = <90000>;
6610 hysteresis = <2000>;
6611 type = "passive";
6612 };
6613
6614 cpu5_bottom_alert1: trip-point1 {
6615 temperature = <95000>;
6616 hysteresis = <2000>;
6617 type = "passive";
6618 };
6619
6620 cpu5_bottom_crit: cpu-crit {
6621 temperature = <110000>;
6622 hysteresis = <1000>;
6623 type = "critical";
6624 };
6625 };
6626
6627 cooling-maps {
6628 map0 {
6629 trip = <&cpu5_bottom_alert0>;
6630 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6631 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6632 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6633 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6634 };
6635 map1 {
6636 trip = <&cpu5_bottom_alert1>;
6637 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6638 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6639 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6640 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6641 };
6642 };
6643 };
6644
6645 cpu6-bottom-thermal {
6646 polling-delay-passive = <250>;
6647 polling-delay = <1000>;
6648
6649 thermal-sensors = <&tsens0 13>;
6650
6651 trips {
6652 cpu6_bottom_alert0: trip-point0 {
6653 temperature = <90000>;
6654 hysteresis = <2000>;
6655 type = "passive";
6656 };
6657
6658 cpu6_bottom_alert1: trip-point1 {
6659 temperature = <95000>;
6660 hysteresis = <2000>;
6661 type = "passive";
6662 };
6663
6664 cpu6_bottom_crit: cpu-crit {
6665 temperature = <110000>;
6666 hysteresis = <1000>;
6667 type = "critical";
6668 };
6669 };
6670
6671 cooling-maps {
6672 map0 {
6673 trip = <&cpu6_bottom_alert0>;
6674 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6675 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6676 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6677 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6678 };
6679 map1 {
6680 trip = <&cpu6_bottom_alert1>;
6681 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6682 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6683 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6684 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6685 };
6686 };
6687 };
6688
6689 cpu7-bottom-thermal {
6690 polling-delay-passive = <250>;
6691 polling-delay = <1000>;
6692
6693 thermal-sensors = <&tsens0 14>;
6694
6695 trips {
6696 cpu7_bottom_alert0: trip-point0 {
6697 temperature = <90000>;
6698 hysteresis = <2000>;
6699 type = "passive";
6700 };
6701
6702 cpu7_bottom_alert1: trip-point1 {
6703 temperature = <95000>;
6704 hysteresis = <2000>;
6705 type = "passive";
6706 };
6707
6708 cpu7_bottom_crit: cpu-crit {
6709 temperature = <110000>;
6710 hysteresis = <1000>;
6711 type = "critical";
6712 };
6713 };
6714
6715 cooling-maps {
6716 map0 {
6717 trip = <&cpu7_bottom_alert0>;
6718 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6719 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6720 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6721 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6722 };
6723 map1 {
6724 trip = <&cpu7_bottom_alert1>;
6725 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6726 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6727 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6728 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6729 };
6730 };
6731 };
6732
6733 aoss0-thermal {
6734 polling-delay-passive = <250>;
6735 polling-delay = <1000>;
6736
6737 thermal-sensors = <&tsens0 0>;
6738
6739 trips {
6740 aoss0_alert0: trip-point0 {
6741 temperature = <90000>;
6742 hysteresis = <2000>;
6743 type = "hot";
6744 };
6745 };
6746 };
6747
6748 cluster0-thermal {
6749 polling-delay-passive = <250>;
6750 polling-delay = <1000>;
6751
6752 thermal-sensors = <&tsens0 5>;
6753
6754 trips {
6755 cluster0_alert0: trip-point0 {
6756 temperature = <90000>;
6757 hysteresis = <2000>;
6758 type = "hot";
6759 };
6760 cluster0_crit: cluster0_crit {
6761 temperature = <110000>;
6762 hysteresis = <2000>;
6763 type = "critical";
6764 };
6765 };
6766 };
6767
6768 cluster1-thermal {
6769 polling-delay-passive = <250>;
6770 polling-delay = <1000>;
6771
6772 thermal-sensors = <&tsens0 6>;
6773
6774 trips {
6775 cluster1_alert0: trip-point0 {
6776 temperature = <90000>;
6777 hysteresis = <2000>;
6778 type = "hot";
6779 };
6780 cluster1_crit: cluster1_crit {
6781 temperature = <110000>;
6782 hysteresis = <2000>;
6783 type = "critical";
6784 };
6785 };
6786 };
6787
6788 gpu-top-thermal {
6789 polling-delay-passive = <250>;
6790 polling-delay = <1000>;
6791
6792 thermal-sensors = <&tsens0 15>;
6793
6794 trips {
6795 gpu1_alert0: trip-point0 {
6796 temperature = <90000>;
6797 hysteresis = <2000>;
6798 type = "hot";
6799 };
6800 };
6801 };
6802
6803 aoss1-thermal {
6804 polling-delay-passive = <250>;
6805 polling-delay = <1000>;
6806
6807 thermal-sensors = <&tsens1 0>;
6808
6809 trips {
6810 aoss1_alert0: trip-point0 {
6811 temperature = <90000>;
6812 hysteresis = <2000>;
6813 type = "hot";
6814 };
6815 };
6816 };
6817
6818 wlan-thermal {
6819 polling-delay-passive = <250>;
6820 polling-delay = <1000>;
6821
6822 thermal-sensors = <&tsens1 1>;
6823
6824 trips {
6825 wlan_alert0: trip-point0 {
6826 temperature = <90000>;
6827 hysteresis = <2000>;
6828 type = "hot";
6829 };
6830 };
6831 };
6832
6833 video-thermal {
6834 polling-delay-passive = <250>;
6835 polling-delay = <1000>;
6836
6837 thermal-sensors = <&tsens1 2>;
6838
6839 trips {
6840 video_alert0: trip-point0 {
6841 temperature = <90000>;
6842 hysteresis = <2000>;
6843 type = "hot";
6844 };
6845 };
6846 };
6847
6848 mem-thermal {
6849 polling-delay-passive = <250>;
6850 polling-delay = <1000>;
6851
6852 thermal-sensors = <&tsens1 3>;
6853
6854 trips {
6855 mem_alert0: trip-point0 {
6856 temperature = <90000>;
6857 hysteresis = <2000>;
6858 type = "hot";
6859 };
6860 };
6861 };
6862
6863 q6-hvx-thermal {
6864 polling-delay-passive = <250>;
6865 polling-delay = <1000>;
6866
6867 thermal-sensors = <&tsens1 4>;
6868
6869 trips {
6870 q6_hvx_alert0: trip-point0 {
6871 temperature = <90000>;
6872 hysteresis = <2000>;
6873 type = "hot";
6874 };
6875 };
6876 };
6877
6878 camera-thermal {
6879 polling-delay-passive = <250>;
6880 polling-delay = <1000>;
6881
6882 thermal-sensors = <&tsens1 5>;
6883
6884 trips {
6885 camera_alert0: trip-point0 {
6886 temperature = <90000>;
6887 hysteresis = <2000>;
6888 type = "hot";
6889 };
6890 };
6891 };
6892
6893 compute-thermal {
6894 polling-delay-passive = <250>;
6895 polling-delay = <1000>;
6896
6897 thermal-sensors = <&tsens1 6>;
6898
6899 trips {
6900 compute_alert0: trip-point0 {
6901 temperature = <90000>;
6902 hysteresis = <2000>;
6903 type = "hot";
6904 };
6905 };
6906 };
6907
6908 npu-thermal {
6909 polling-delay-passive = <250>;
6910 polling-delay = <1000>;
6911
6912 thermal-sensors = <&tsens1 7>;
6913
6914 trips {
6915 npu_alert0: trip-point0 {
6916 temperature = <90000>;
6917 hysteresis = <2000>;
6918 type = "hot";
6919 };
6920 };
6921 };
6922
6923 gpu-bottom-thermal {
6924 polling-delay-passive = <250>;
6925 polling-delay = <1000>;
6926
6927 thermal-sensors = <&tsens1 8>;
6928
6929 trips {
6930 gpu2_alert0: trip-point0 {
6931 temperature = <90000>;
6932 hysteresis = <2000>;
6933 type = "hot";
6934 };
6935 };
6936 };
6937 };
6938};