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git01.mediatek.com / filogic / uboot / a52d20723b7f36fae0e0061c335328b6694b08c5 / . / dts / upstream / src / arm / nxp / imx / imx7ulp.dtsi
blob: ac338320ac1d7c309292ee7eba9baa1ee16f878e [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
5 * Dong Aisheng <aisheng.dong@nxp.com>
6 */
7
8#include <dt-bindings/clock/imx7ulp-clock.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12#include "imx7ulp-pinfunc.h"
13
14/ {
15 interrupt-parent = <&intc>;
16
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 gpio0 = &gpio_ptc;
22 gpio1 = &gpio_ptd;
23 gpio2 = &gpio_pte;
24 gpio3 = &gpio_ptf;
25 i2c0 = &lpi2c6;
26 i2c1 = &lpi2c7;
27 mmc0 = &usdhc0;
28 mmc1 = &usdhc1;
29 serial0 = &lpuart4;
30 serial1 = &lpuart5;
31 serial2 = &lpuart6;
32 serial3 = &lpuart7;
33 usbphy0 = &usbphy1;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@f00 {
41 compatible = "arm,cortex-a7";
42 device_type = "cpu";
43 reg = <0xf00>;
44 };
45 };
46
47 intc: interrupt-controller@40021000 {
48 compatible = "arm,cortex-a7-gic";
49 #interrupt-cells = <3>;
50 interrupt-controller;
51 reg = <0x40021000 0x1000>,
52 <0x40022000 0x1000>;
53 };
54
55 rosc: clock-rosc {
56 compatible = "fixed-clock";
57 clock-frequency = <32768>;
58 clock-output-names = "rosc";
59 #clock-cells = <0>;
60 };
61
62 sosc: clock-sosc {
63 compatible = "fixed-clock";
64 clock-frequency = <24000000>;
65 clock-output-names = "sosc";
66 #clock-cells = <0>;
67 };
68
69 sirc: clock-sirc {
70 compatible = "fixed-clock";
71 clock-frequency = <16000000>;
72 clock-output-names = "sirc";
73 #clock-cells = <0>;
74 };
75
76 firc: clock-firc {
77 compatible = "fixed-clock";
78 clock-frequency = <48000000>;
79 clock-output-names = "firc";
80 #clock-cells = <0>;
81 };
82
83 upll: clock-upll {
84 compatible = "fixed-clock";
85 clock-frequency = <480000000>;
86 clock-output-names = "upll";
87 #clock-cells = <0>;
88 };
89
90 ahbbridge0: bus@40000000 {
91 compatible = "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 reg = <0x40000000 0x800000>;
95 ranges;
96
97 edma1: dma-controller@40080000 {
98 #dma-cells = <2>;
99 compatible = "fsl,imx7ulp-edma";
100 reg = <0x40080000 0x2000>,
101 <0x40210000 0x1000>;
102 dma-channels = <32>;
103 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
120 clock-names = "dma", "dmamux0";
121 clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
122 <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
123 };
124
125 crypto: crypto@40240000 {
126 compatible = "fsl,sec-v4.0";
127 #address-cells = <1>;
128 #size-cells = <1>;
129 reg = <0x40240000 0x10000>;
130 ranges = <0 0x40240000 0x10000>;
131 clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
132 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
133 clock-names = "aclk", "ipg";
134
135 sec_jr0: jr@1000 {
136 compatible = "fsl,sec-v4.0-job-ring";
137 reg = <0x1000 0x1000>;
138 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
139 };
140
141 sec_jr1: jr@2000 {
142 compatible = "fsl,sec-v4.0-job-ring";
143 reg = <0x2000 0x1000>;
144 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
145 };
146 };
147
148 lpuart4: serial@402d0000 {
149 compatible = "fsl,imx7ulp-lpuart";
150 reg = <0x402d0000 0x1000>;
151 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
153 clock-names = "ipg";
154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
157 status = "disabled";
158 };
159
160 lpuart5: serial@402e0000 {
161 compatible = "fsl,imx7ulp-lpuart";
162 reg = <0x402e0000 0x1000>;
163 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
165 clock-names = "ipg";
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
169 status = "disabled";
170 };
171
172 tpm4: pwm@40250000 {
173 compatible = "fsl,imx7ulp-pwm";
174 reg = <0x40250000 0x1000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
177 clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
178 #pwm-cells = <3>;
179 status = "disabled";
180 };
181
182 tpm5: tpm@40260000 {
183 compatible = "fsl,imx7ulp-tpm";
184 reg = <0x40260000 0x1000>;
185 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
187 <&pcc2 IMX7ULP_CLK_LPTPM5>;
188 clock-names = "ipg", "per";
189 };
190
191 usbotg1: usb@40330000 {
192 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
193 reg = <0x40330000 0x200>;
194 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&pcc2 IMX7ULP_CLK_USB0>;
196 phys = <&usbphy1>;
197 fsl,usbmisc = <&usbmisc1 0>;
198 ahb-burst-config = <0x0>;
199 tx-burst-size-dword = <0x8>;
200 rx-burst-size-dword = <0x8>;
201 status = "disabled";
202 };
203
204 usbmisc1: usbmisc@40330200 {
205 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc",
206 "fsl,imx6q-usbmisc";
207 #index-cells = <1>;
208 reg = <0x40330200 0x200>;
209 };
210
211 usbphy1: usb-phy@40350000 {
212 compatible = "fsl,imx7ulp-usbphy";
213 reg = <0x40350000 0x1000>;
214 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
216 #phy-cells = <0>;
217 };
218
219 usdhc0: mmc@40370000 {
220 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
221 reg = <0x40370000 0x10000>;
222 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
224 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
225 <&pcc2 IMX7ULP_CLK_USDHC0>;
226 clock-names = "ipg", "ahb", "per";
227 bus-width = <4>;
228 fsl,tuning-start-tap = <20>;
229 fsl,tuning-step = <2>;
230 status = "disabled";
231 };
232
233 usdhc1: mmc@40380000 {
234 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
235 reg = <0x40380000 0x10000>;
236 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
238 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
239 <&pcc2 IMX7ULP_CLK_USDHC1>;
240 clock-names = "ipg", "ahb", "per";
241 bus-width = <4>;
242 fsl,tuning-start-tap = <20>;
243 fsl,tuning-step = <2>;
244 status = "disabled";
245 };
246
247 scg1: clock-controller@403e0000 {
248 compatible = "fsl,imx7ulp-scg1";
249 reg = <0x403e0000 0x10000>;
250 clocks = <&rosc>, <&sosc>, <&sirc>,
251 <&firc>, <&upll>;
252 clock-names = "rosc", "sosc", "sirc",
253 "firc", "upll";
254 #clock-cells = <1>;
255 };
256
257 wdog1: watchdog@403d0000 {
258 compatible = "fsl,imx7ulp-wdt";
259 reg = <0x403d0000 0x10000>;
260 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
262 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
263 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
264 timeout-sec = <40>;
265 };
266
267 pcc2: clock-controller@403f0000 {
268 compatible = "fsl,imx7ulp-pcc2";
269 reg = <0x403f0000 0x10000>;
270 #clock-cells = <1>;
271 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
272 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
273 <&scg1 IMX7ULP_CLK_DDR_DIV>,
274 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
275 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
276 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
277 <&scg1 IMX7ULP_CLK_UPLL>,
278 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
279 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
280 <&scg1 IMX7ULP_CLK_ROSC>,
281 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
282 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
283 "apll_pfd2", "apll_pfd1", "apll_pfd0",
284 "upll", "sosc_bus_clk",
285 "firc_bus_clk", "rosc", "spll_bus_clk";
286 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
287 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
288 };
289
290 smc1: clock-controller@40410000 {
291 compatible = "fsl,imx7ulp-smc1";
292 reg = <0x40410000 0x1000>;
293 #clock-cells = <1>;
294 clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
295 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
296 clock-names = "divcore", "hsrun_divcore";
297 };
298
299 pcc3: clock-controller@40b30000 {
300 compatible = "fsl,imx7ulp-pcc3";
301 reg = <0x40b30000 0x10000>;
302 #clock-cells = <1>;
303 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
304 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
305 <&scg1 IMX7ULP_CLK_DDR_DIV>,
306 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
307 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
308 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
309 <&scg1 IMX7ULP_CLK_UPLL>,
310 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
311 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
312 <&scg1 IMX7ULP_CLK_ROSC>,
313 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
314 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
315 "apll_pfd2", "apll_pfd1", "apll_pfd0",
316 "upll", "sosc_bus_clk",
317 "firc_bus_clk", "rosc", "spll_bus_clk";
318 };
319 };
320
321 ahbbridge1: bus@40800000 {
322 compatible = "simple-bus";
323 #address-cells = <1>;
324 #size-cells = <1>;
325 reg = <0x40800000 0x800000>;
326 ranges;
327
328 lpi2c6: i2c@40a40000 {
329 compatible = "fsl,imx7ulp-lpi2c";
330 reg = <0x40a40000 0x10000>;
331 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>,
333 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
334 clock-names = "per", "ipg";
335 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
336 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
337 assigned-clock-rates = <48000000>;
338 status = "disabled";
339 };
340
341 lpi2c7: i2c@40a50000 {
342 compatible = "fsl,imx7ulp-lpi2c";
343 reg = <0x40a50000 0x10000>;
344 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>,
346 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
347 clock-names = "per", "ipg";
348 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
349 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
350 assigned-clock-rates = <48000000>;
351 status = "disabled";
352 };
353
354 lpuart6: serial@40a60000 {
355 compatible = "fsl,imx7ulp-lpuart";
356 reg = <0x40a60000 0x1000>;
357 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
359 clock-names = "ipg";
360 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
361 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
362 assigned-clock-rates = <48000000>;
363 status = "disabled";
364 };
365
366 lpuart7: serial@40a70000 {
367 compatible = "fsl,imx7ulp-lpuart";
368 reg = <0x40a70000 0x1000>;
369 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
371 clock-names = "ipg";
372 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
373 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
374 assigned-clock-rates = <48000000>;
375 status = "disabled";
376 };
377
378 memory-controller@40ab0000 {
379 compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
380 reg = <0x40ab0000 0x1000>;
381 clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
382 };
383
384 iomuxc1: pinctrl@40ac0000 {
385 compatible = "fsl,imx7ulp-iomuxc1";
386 reg = <0x40ac0000 0x1000>;
387 };
388
389 gpio_ptc: gpio@40ae0000 {
390 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
391 reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
392 gpio-controller;
393 #gpio-cells = <2>;
394 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
398 <&pcc3 IMX7ULP_CLK_PCTLC>;
399 clock-names = "gpio", "port";
400 gpio-ranges = <&iomuxc1 0 0 20>;
401 };
402
403 gpio_ptd: gpio@40af0000 {
404 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
405 reg = <0x40af0000 0x1000 0x400f0040 0x40>;
406 gpio-controller;
407 #gpio-cells = <2>;
408 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
411 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
412 <&pcc3 IMX7ULP_CLK_PCTLD>;
413 clock-names = "gpio", "port";
414 gpio-ranges = <&iomuxc1 0 32 12>;
415 };
416
417 gpio_pte: gpio@40b00000 {
418 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
419 reg = <0x40b00000 0x1000 0x400f0080 0x40>;
420 gpio-controller;
421 #gpio-cells = <2>;
422 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
423 interrupt-controller;
424 #interrupt-cells = <2>;
425 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
426 <&pcc3 IMX7ULP_CLK_PCTLE>;
427 clock-names = "gpio", "port";
428 gpio-ranges = <&iomuxc1 0 64 16>;
429 };
430
431 gpio_ptf: gpio@40b10000 {
432 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
433 reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
434 gpio-controller;
435 #gpio-cells = <2>;
436 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
437 interrupt-controller;
438 #interrupt-cells = <2>;
439 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
440 <&pcc3 IMX7ULP_CLK_PCTLF>;
441 clock-names = "gpio", "port";
442 gpio-ranges = <&iomuxc1 0 96 20>;
443 };
444 };
445
446 m4aips1: bus@41080000 {
447 compatible = "simple-bus";
448 #address-cells = <1>;
449 #size-cells = <1>;
450 reg = <0x41080000 0x80000>;
451 ranges;
452
453 sim: sim@410a3000 {
454 compatible = "fsl,imx7ulp-sim", "syscon";
455 reg = <0x410a3000 0x1000>;
456 };
457
458 ocotp: efuse@410a6000 {
459 compatible = "fsl,imx7ulp-ocotp", "syscon";
460 reg = <0x410a6000 0x4000>;
461 clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
462 #address-cells = <1>;
463 #size-cells = <1>;
464 };
465 };
466};