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git01.mediatek.com / filogic / uboot / a52d20723b7f36fae0e0061c335328b6694b08c5 / . / dts / upstream / src / arm / nxp / imx / imx6qdl-nit6xlite.dtsi
blob: f2542d725ce7db45b4a2e9ff19dea024745c2f52 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Copyright 2015 Boundary Devices, Inc.
4 */
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/input/input.h>
7
8/ {
9 chosen {
10 stdout-path = &uart2;
11 };
12
13 memory@10000000 {
14 device_type = "memory";
15 reg = <0x10000000 0x20000000>;
16 };
17
18 reg_2p5v: regulator-2p5v {
19 compatible = "regulator-fixed";
20 regulator-name = "2P5V";
21 regulator-min-microvolt = <2500000>;
22 regulator-max-microvolt = <2500000>;
23 regulator-always-on;
24 };
25
26 reg_3p3v: regulator-3p3v {
27 compatible = "regulator-fixed";
28 regulator-name = "3P3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 regulator-always-on;
32 };
33
34 reg_usb_otg_vbus: regulator-usb-otg-vbus {
35 compatible = "regulator-fixed";
36 regulator-name = "usb_otg_vbus";
37 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <5000000>;
39 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
40 enable-active-high;
41 };
42
43 reg_wlan_vmmc: regulator-wlan-vmmc {
44 compatible = "regulator-fixed";
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_wlan_vmmc>;
47 regulator-name = "reg_wlan_vmmc";
48 regulator-min-microvolt = <1800000>;
49 regulator-max-microvolt = <1800000>;
50 gpio = <&gpio6 7 GPIO_ACTIVE_HIGH>;
51 startup-delay-us = <70000>;
52 enable-active-high;
53 };
54
55 gpio-keys {
56 compatible = "gpio-keys";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_gpio_keys>;
59
60 home {
61 label = "Home";
62 gpios = <&gpio7 13 IRQ_TYPE_LEVEL_LOW>;
63 linux,code = <102>;
64 };
65
66 back {
67 label = "Back";
68 gpios = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>;
69 linux,code = <158>;
70 };
71 };
72
73 leds {
74 compatible = "gpio-leds";
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_leds>;
77
78 led-j14-pin1 {
79 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
80 retain-state-suspended;
81 default-state = "off";
82 };
83
84 led-j14-pin3 {
85 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
86 retain-state-suspended;
87 default-state = "off";
88 };
89
90 led-j14-pins8-9 {
91 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
92 retain-state-suspended;
93 default-state = "off";
94 };
95
96 led-j46-pin2 {
97 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
98 retain-state-suspended;
99 default-state = "off";
100 };
101
102 led-j46-pin3 {
103 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
104 retain-state-suspended;
105 default-state = "off";
106 };
107 };
108
109 backlight-lcd {
110 compatible = "pwm-backlight";
111 pwms = <&pwm1 0 5000000>;
112 brightness-levels = <0 4 8 16 32 64 128 255>;
113 default-brightness-level = <7>;
114 power-supply = <&reg_3p3v>;
115 status = "okay";
116 };
117
118 backlight_lvds0: backlight-lvds0 {
119 compatible = "pwm-backlight";
120 pwms = <&pwm4 0 5000000>;
121 brightness-levels = <0 4 8 16 32 64 128 255>;
122 default-brightness-level = <7>;
123 power-supply = <&reg_3p3v>;
124 status = "okay";
125 };
126
127 panel-lvds0 {
128 compatible = "hannstar,hsd100pxn1";
129 backlight = <&backlight_lvds0>;
130
131 port {
132 panel_in_lvds0: endpoint {
133 remote-endpoint = <&lvds0_out>;
134 };
135 };
136 };
137
138 sound {
139 compatible = "fsl,imx6dl-nit6xlite-sgtl5000",
140 "fsl,imx-audio-sgtl5000";
141 model = "imx6dl-nit6xlite-sgtl5000";
142 ssi-controller = <&ssi1>;
143 audio-codec = <&codec>;
144 audio-routing =
145 "MIC_IN", "Mic Jack",
146 "Mic Jack", "Mic Bias",
147 "Headphone Jack", "HP_OUT";
148 mux-int-port = <1>;
149 mux-ext-port = <3>;
150 };
151};
152
153&audmux {
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_audmux>;
156 status = "okay";
157};
158
159&clks {
160 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
161 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
162 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
163 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
164};
165
166&ecspi1 {
167 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_ecspi1>;
170 status = "okay";
171
172 flash: flash@0 {
173 compatible = "microchip,sst25vf016b";
174 spi-max-frequency = <20000000>;
175 reg = <0>;
176 };
177};
178
179&fec {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_enet>;
182 phy-mode = "rgmii";
183 phy-handle = <&ethphy>;
184 phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
185 /delete-property/ interrupts;
186 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
187 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
188 fsl,err006687-workaround-present;
189 status = "okay";
190
191 mdio {
192 #address-cells = <1>;
193 #size-cells = <0>;
194
195 ethphy: ethernet-phy {
196 compatible = "ethernet-phy-ieee802.3-c22";
197 txen-skew-ps = <0>;
198 txc-skew-ps = <3000>;
199 rxdv-skew-ps = <0>;
200 rxc-skew-ps = <3000>;
201 rxd0-skew-ps = <0>;
202 rxd1-skew-ps = <0>;
203 rxd2-skew-ps = <0>;
204 rxd3-skew-ps = <0>;
205 txd0-skew-ps = <0>;
206 txd1-skew-ps = <0>;
207 txd2-skew-ps = <0>;
208 txd3-skew-ps = <0>;
209 };
210 };
211};
212
213&hdmi {
214 ddc-i2c-bus = <&i2c2>;
215 status = "okay";
216};
217
218&i2c1 {
219 clock-frequency = <100000>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_i2c1>;
222 status = "okay";
223
224 codec: sgtl5000@a {
225 compatible = "fsl,sgtl5000";
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_sgtl5000>;
228 reg = <0x0a>;
229 #sound-dai-cells = <0>;
230 clocks = <&clks IMX6QDL_CLK_CKO>;
231 VDDA-supply = <&reg_2p5v>;
232 VDDIO-supply = <&reg_3p3v>;
233 };
234};
235
236&i2c2 {
237 clock-frequency = <100000>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_i2c2>;
240 status = "okay";
241};
242
243&i2c3 {
244 clock-frequency = <100000>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_i2c3>;
247 status = "okay";
248
249 touchscreen@4 {
250 compatible = "eeti,egalax_ts";
251 reg = <0x04>;
252 interrupt-parent = <&gpio1>;
253 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
254 wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
255 };
256
257 touchscreen@38 {
258 compatible = "edt,edt-ft5x06";
259 reg = <0x38>;
260 interrupt-parent = <&gpio1>;
261 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
262 wakeup-source;
263 };
264
265 rtc@6f {
266 compatible = "isil,isl1208";
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_rtc>;
269 reg = <0x6f>;
270 interrupts-extended = <&gpio2 26 IRQ_TYPE_LEVEL_LOW>;
271 };
272};
273
274&iomuxc {
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_j10>;
277 pinctrl-1 = <&pinctrl_j28>;
278
279 imx6dl-nit6xlite {
280 pinctrl_audmux: audmuxgrp {
281 fsl,pins = <
282 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
283 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
284 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
285 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
286 >;
287 };
288
289 pinctrl_ecspi1: ecspi1grp {
290 fsl,pins = <
291 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
292 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
293 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
294 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
295 >;
296 };
297
298 pinctrl_enet: enetgrp {
299 fsl,pins = <
300 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
301 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
302 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
303 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
304 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
305 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
306 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
307 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
308 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
309 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
310 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
311 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
312 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
313 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
314 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
315 /* Phy reset */
316 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0
317 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
318 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
319 >;
320 };
321
322 pinctrl_gpio_keys: gpio-keysgrp {
323 fsl,pins = <
324 /* Home Button: J14 pin 5 */
325 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
326 /* Back Button: J14 pin 7 */
327 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
328 >;
329 };
330
331 pinctrl_i2c1: i2c1grp {
332 fsl,pins = <
333 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
334 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
335 >;
336 };
337
338 pinctrl_i2c2: i2c2grp {
339 fsl,pins = <
340 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
341 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
342 >;
343 };
344
345 pinctrl_i2c3: i2c3grp {
346 fsl,pins = <
347 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
348 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
349 /* Touch IRQ: J7 pin 4 */
350 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
351 /* tcs2004 IRQ */
352 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
353 /* tsc2004 reset */
354 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x0b0b0
355 >;
356 };
357
358 pinctrl_j10: j10grp {
359 fsl,pins = <
360 /* Broadcom WiFi module pins */
361 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
362 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
363 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
364 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
365 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
366 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
367 MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0
368 >;
369 };
370
371 pinctrl_j28: j28grp {
372 fsl,pins = <
373 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
374 >;
375 };
376
377 pinctrl_leds: ledsgrp {
378 fsl,pins = <
379 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0b0b0
380 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x0b0b0
381 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x030b0
382 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b0b0
383 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0
384 >;
385 };
386
387 pinctrl_pwm1: pwm1grp {
388 fsl,pins = <
389 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
390 >;
391 };
392
393 pinctrl_pwm3: pwm3grp {
394 fsl,pins = <
395 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
396 >;
397 };
398
399 pinctrl_pwm4: pwm4grp {
400 fsl,pins = <
401 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
402 >;
403 };
404
405 pinctrl_wlan_vmmc: wlan-vmmcgrp {
406 fsl,pins = <
407 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b0
408 >;
409 };
410
411 pinctrl_rtc: rtcgrp {
412 fsl,pins = <
413 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0
414 >;
415 };
416
417 pinctrl_sgtl5000: sgtl5000grp {
418 fsl,pins = <
419 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
420 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
421 >;
422 };
423
424 pinctrl_uart1: uart1grp {
425 fsl,pins = <
426 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
427 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
428 >;
429 };
430
431 pinctrl_uart2: uart2grp {
432 fsl,pins = <
433 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
434 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
435 >;
436 };
437
438 pinctrl_uart3: uart3grp {
439 fsl,pins = <
440 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
441 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
442 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
443 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
444 >;
445 };
446
447 pinctrl_usbotg: usbotggrp {
448 fsl,pins = <
449 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
450 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
451 /* power enable, high active */
452 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
453 >;
454 };
455
456 pinctrl_usdhc2: usdhc2grp {
457 fsl,pins = <
458 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
459 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
460 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
461 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
462 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
463 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
464 >;
465 };
466
467 pinctrl_usdhc3: usdhc3grp {
468 fsl,pins = <
469 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
470 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
471 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
472 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
473 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
474 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
475 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
476 >;
477 };
478 };
479};
480
481&ldb {
482 status = "okay";
483
484 lvds-channel@0 {
485 status = "okay";
486
487 port@4 {
488 reg = <4>;
489
490 lvds0_out: endpoint {
491 remote-endpoint = <&panel_in_lvds0>;
492 };
493 };
494 };
495};
496
497&pcie {
498 status = "okay";
499};
500
501&pwm1 {
502 #pwm-cells = <2>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&pinctrl_pwm1>;
505 status = "okay";
506};
507
508&pwm3 {
509 pinctrl-names = "default";
510 pinctrl-0 = <&pinctrl_pwm3>;
511 status = "okay";
512};
513
514&pwm4 {
515 #pwm-cells = <2>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&pinctrl_pwm4>;
518 status = "okay";
519};
520
521&ssi1 {
522 status = "okay";
523};
524
525&uart1 {
526 pinctrl-names = "default";
527 pinctrl-0 = <&pinctrl_uart1>;
528 status = "okay";
529};
530
531&uart2 {
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_uart2>;
534 status = "okay";
535};
536
537&uart3 {
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_uart3>;
540 uart-has-rtscts;
541 status = "okay";
542};
543
544&usbh1 {
545 status = "okay";
546};
547
548&usbotg {
549 vbus-supply = <&reg_usb_otg_vbus>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&pinctrl_usbotg>;
552 disable-over-current;
553 status = "okay";
554};
555
556&usdhc2 {
557 pinctrl-names = "default";
558 pinctrl-0 = <&pinctrl_usdhc2>;
559 bus-width = <4>;
560 non-removable;
561 vmmc-supply = <&reg_3p3v>;
562 vqmmc-supply = <&reg_wlan_vmmc>;
563 cap-power-off-card;
564 keep-power-in-suspend;
565 status = "okay";
566};
567
568&usdhc3 {
569 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_usdhc3>;
571 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
572 vmmc-supply = <&reg_3p3v>;
573 status = "okay";
574};