| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: MediaTek Smart Voltage Scaling (SVS) |
| 8 | |
| 9 | maintainers: |
| 10 | - Roger Lu <roger.lu@mediatek.com> |
| 11 | - Matthias Brugger <matthias.bgg@gmail.com> |
| 12 | - Kevin Hilman <khilman@kernel.org> |
| 13 | |
| 14 | description: |+ |
| 15 | The SVS engine is a piece of hardware which has several |
| 16 | controllers(banks) for calculating suitable voltage to |
| 17 | different power domains(CPU/GPU/CCI) according to |
| 18 | chip process corner, temperatures and other factors. Then DVFS |
| 19 | driver could apply SVS bank voltage to PMIC/Buck. |
| 20 | |
| 21 | properties: |
| 22 | compatible: |
| 23 | enum: |
| 24 | - mediatek,mt8183-svs |
| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 25 | - mediatek,mt8186-svs |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 26 | - mediatek,mt8188-svs |
| 27 | - mediatek,mt8192-svs |
| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 28 | - mediatek,mt8195-svs |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 29 | |
| 30 | reg: |
| 31 | maxItems: 1 |
| 32 | description: Address range of the MTK SVS controller. |
| 33 | |
| 34 | interrupts: |
| 35 | maxItems: 1 |
| 36 | |
| 37 | clocks: |
| 38 | maxItems: 1 |
| 39 | description: Main clock for MTK SVS controller to work. |
| 40 | |
| 41 | clock-names: |
| 42 | const: main |
| 43 | |
| 44 | nvmem-cells: |
| 45 | minItems: 1 |
| 46 | description: |
| 47 | Phandle to the calibration data provided by a nvmem device. |
| 48 | items: |
| 49 | - description: SVS efuse for SVS controller |
| 50 | - description: Thermal efuse for SVS controller |
| 51 | |
| 52 | nvmem-cell-names: |
| 53 | items: |
| 54 | - const: svs-calibration-data |
| 55 | - const: t-calibration-data |
| 56 | |
| 57 | resets: |
| 58 | maxItems: 1 |
| 59 | |
| 60 | reset-names: |
| 61 | items: |
| 62 | - const: svs_rst |
| 63 | |
| 64 | required: |
| 65 | - compatible |
| 66 | - reg |
| 67 | - interrupts |
| 68 | - clocks |
| 69 | - clock-names |
| 70 | - nvmem-cells |
| 71 | - nvmem-cell-names |
| 72 | |
| 73 | additionalProperties: false |
| 74 | |
| 75 | examples: |
| 76 | - | |
| 77 | #include <dt-bindings/clock/mt8183-clk.h> |
| 78 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 79 | #include <dt-bindings/interrupt-controller/irq.h> |
| 80 | |
| 81 | soc { |
| 82 | #address-cells = <2>; |
| 83 | #size-cells = <2>; |
| 84 | |
| 85 | svs@1100b000 { |
| 86 | compatible = "mediatek,mt8183-svs"; |
| 87 | reg = <0 0x1100b000 0 0x1000>; |
| 88 | interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; |
| 89 | clocks = <&infracfg CLK_INFRA_THERM>; |
| 90 | clock-names = "main"; |
| 91 | nvmem-cells = <&svs_calibration>, <&thermal_calibration>; |
| 92 | nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; |
| 93 | }; |
| 94 | }; |