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git01.mediatek.com / filogic / uboot / a52d20723b7f36fae0e0061c335328b6694b08c5 / . / dts / upstream / Bindings / pci / rcar-pci-host.yaml
blob: b6a7cb32f61e5d4f1d0cff979bf3e7ecd46116fb [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 Renesas Electronics Corp.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Renesas R-Car PCIe Host
9
10maintainers:
11 - Marek Vasut <marek.vasut+renesas@gmail.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13
14allOf:
15 - $ref: pci-bus.yaml#
16
17properties:
18 compatible:
19 oneOf:
20 - const: renesas,pcie-r8a7779 # R-Car H1
21 - items:
22 - enum:
23 - renesas,pcie-r8a7742 # RZ/G1H
24 - renesas,pcie-r8a7743 # RZ/G1M
25 - renesas,pcie-r8a7744 # RZ/G1N
26 - renesas,pcie-r8a7790 # R-Car H2
27 - renesas,pcie-r8a7791 # R-Car M2-W
28 - renesas,pcie-r8a7793 # R-Car M2-N
29 - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
30 - items:
31 - enum:
32 - renesas,pcie-r8a774a1 # RZ/G2M
33 - renesas,pcie-r8a774b1 # RZ/G2N
34 - renesas,pcie-r8a774c0 # RZ/G2E
35 - renesas,pcie-r8a774e1 # RZ/G2H
36 - renesas,pcie-r8a7795 # R-Car H3
37 - renesas,pcie-r8a7796 # R-Car M3-W
38 - renesas,pcie-r8a77961 # R-Car M3-W+
39 - renesas,pcie-r8a77965 # R-Car M3-N
40 - renesas,pcie-r8a77980 # R-Car V3H
41 - renesas,pcie-r8a77990 # R-Car E3
42 - const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2
43
44 reg:
45 maxItems: 1
46
47 interrupts:
48 minItems: 3
49 maxItems: 3
50
51 clocks:
52 maxItems: 2
53
54 clock-names:
55 items:
56 - const: pcie
57 - const: pcie_bus
58
59 power-domains:
60 maxItems: 1
61
62 resets:
63 maxItems: 1
64
65 phys:
66 maxItems: 1
67
68 phy-names:
69 const: pcie
70
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]71 vpcie1v5-supply:
72 description: The 1.5v regulator to use for PCIe.
73
74 vpcie3v3-supply:
75 description: The 3.3v regulator to use for PCIe.
76
77 vpcie12v-supply:
78 description: The 12v regulator to use for PCIe.
79
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]80required:
81 - compatible
82 - reg
83 - interrupts
84 - clocks
85 - clock-names
86 - power-domains
87
88if:
89 not:
90 properties:
91 compatible:
92 contains:
93 const: renesas,pcie-r8a7779
94then:
95 required:
96 - resets
97
98unevaluatedProperties: false
99
100examples:
101 - |
102 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
103 #include <dt-bindings/interrupt-controller/arm-gic.h>
104 #include <dt-bindings/power/r8a7791-sysc.h>
105
106 soc {
107 #address-cells = <2>;
108 #size-cells = <2>;
109
110 pcie: pcie@fe000000 {
111 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
112 reg = <0 0xfe000000 0 0x80000>;
113 #address-cells = <3>;
114 #size-cells = <2>;
115 bus-range = <0x00 0xff>;
116 device_type = "pci";
117 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
118 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
119 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
120 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
121 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
122 <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
123 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
126 #interrupt-cells = <1>;
127 interrupt-map-mask = <0 0 0 0>;
128 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
130 clock-names = "pcie", "pcie_bus";
131 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
132 resets = <&cpg 319>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]133 vpcie3v3-supply = <&pcie_3v3>;
134 vpcie12v-supply = <&pcie_12v>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]135 };
136 };