Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: NVIDIA Tegra234 NVDEC |
| 8 | |
| 9 | description: | |
| 10 | NVDEC is the hardware video decoder present on NVIDIA Tegra210 |
| 11 | and newer chips. It is located on the Host1x bus and typically |
| 12 | programmed through Host1x channels. |
| 13 | |
| 14 | maintainers: |
| 15 | - Thierry Reding <treding@gmail.com> |
| 16 | - Mikko Perttunen <mperttunen@nvidia.com> |
| 17 | |
| 18 | properties: |
| 19 | $nodename: |
| 20 | pattern: "^nvdec@[0-9a-f]*$" |
| 21 | |
| 22 | compatible: |
| 23 | enum: |
| 24 | - nvidia,tegra234-nvdec |
| 25 | |
| 26 | reg: |
| 27 | maxItems: 1 |
| 28 | |
| 29 | clocks: |
| 30 | maxItems: 3 |
| 31 | |
| 32 | clock-names: |
| 33 | items: |
| 34 | - const: nvdec |
| 35 | - const: fuse |
| 36 | - const: tsec_pka |
| 37 | |
| 38 | resets: |
| 39 | maxItems: 1 |
| 40 | |
| 41 | reset-names: |
| 42 | items: |
| 43 | - const: nvdec |
| 44 | |
| 45 | power-domains: |
| 46 | maxItems: 1 |
| 47 | |
| 48 | iommus: |
| 49 | maxItems: 1 |
| 50 | |
| 51 | dma-coherent: true |
| 52 | |
| 53 | interconnects: |
| 54 | items: |
| 55 | - description: DMA read memory client |
| 56 | - description: DMA write memory client |
| 57 | |
| 58 | interconnect-names: |
| 59 | items: |
| 60 | - const: dma-mem |
| 61 | - const: write |
| 62 | |
| 63 | nvidia,memory-controller: |
| 64 | $ref: /schemas/types.yaml#/definitions/phandle |
| 65 | description: |
| 66 | phandle to the memory controller for determining information for the NVDEC |
| 67 | firmware secure carveout. This carveout is configured by the bootloader and |
| 68 | not accessible to CPU. |
| 69 | |
| 70 | nvidia,bl-manifest-offset: |
| 71 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 72 | description: |
| 73 | Offset to bootloader manifest from beginning of firmware that was configured by |
| 74 | the bootloader. |
| 75 | |
| 76 | nvidia,bl-code-offset: |
| 77 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 78 | description: |
| 79 | Offset to bootloader code section from beginning of firmware that was configured by |
| 80 | the bootloader. |
| 81 | |
| 82 | nvidia,bl-data-offset: |
| 83 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 84 | description: |
| 85 | Offset to bootloader data section from beginning of firmware that was configured by |
| 86 | the bootloader. |
| 87 | |
| 88 | nvidia,os-manifest-offset: |
| 89 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 90 | description: |
| 91 | Offset to operating system manifest from beginning of firmware that was configured by |
| 92 | the bootloader. |
| 93 | |
| 94 | nvidia,os-code-offset: |
| 95 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 96 | description: |
| 97 | Offset to operating system code section from beginning of firmware that was configured by |
| 98 | the bootloader. |
| 99 | |
| 100 | nvidia,os-data-offset: |
| 101 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 102 | description: |
| 103 | Offset to operating system data section from beginning of firmware that was configured |
| 104 | by the bootloader. |
| 105 | |
| 106 | required: |
| 107 | - compatible |
| 108 | - reg |
| 109 | - clocks |
| 110 | - clock-names |
| 111 | - resets |
| 112 | - reset-names |
| 113 | - power-domains |
| 114 | - nvidia,memory-controller |
| 115 | - nvidia,bl-manifest-offset |
| 116 | - nvidia,bl-code-offset |
| 117 | - nvidia,bl-data-offset |
| 118 | - nvidia,os-manifest-offset |
| 119 | - nvidia,os-code-offset |
| 120 | - nvidia,os-data-offset |
| 121 | |
| 122 | additionalProperties: false |
| 123 | |
| 124 | examples: |
| 125 | - | |
| 126 | #include <dt-bindings/clock/tegra234-clock.h> |
| 127 | #include <dt-bindings/memory/tegra234-mc.h> |
| 128 | #include <dt-bindings/power/tegra234-powergate.h> |
| 129 | #include <dt-bindings/reset/tegra234-reset.h> |
| 130 | |
| 131 | nvdec@15480000 { |
| 132 | compatible = "nvidia,tegra234-nvdec"; |
| 133 | reg = <0x15480000 0x00040000>; |
| 134 | clocks = <&bpmp TEGRA234_CLK_NVDEC>, |
| 135 | <&bpmp TEGRA234_CLK_FUSE>, |
| 136 | <&bpmp TEGRA234_CLK_TSEC_PKA>; |
| 137 | clock-names = "nvdec", "fuse", "tsec_pka"; |
| 138 | resets = <&bpmp TEGRA234_RESET_NVDEC>; |
| 139 | reset-names = "nvdec"; |
| 140 | power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; |
| 141 | interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, |
| 142 | <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; |
| 143 | interconnect-names = "dma-mem", "write"; |
| 144 | iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; |
| 145 | dma-coherent; |
| 146 | |
| 147 | nvidia,memory-controller = <&mc>; |
| 148 | |
| 149 | /* Placeholder values, to be replaced with values from overlay */ |
| 150 | nvidia,bl-manifest-offset = <0>; |
| 151 | nvidia,bl-data-offset = <0>; |
| 152 | nvidia,bl-code-offset = <0>; |
| 153 | nvidia,os-manifest-offset = <0>; |
| 154 | nvidia,os-data-offset = <0>; |
| 155 | nvidia,os-code-offset = <0>; |
| 156 | }; |