| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcomm Technologies Inc GPI DMA controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Vinod Koul <vkoul@kernel.org> |
| 11 | |
| 12 | description: | |
| 13 | QCOM GPI DMA controller provides DMA capabilities for |
| 14 | peripheral buses such as I2C, UART, and SPI. |
| 15 | |
| 16 | allOf: |
| 17 | - $ref: dma-controller.yaml# |
| 18 | |
| 19 | properties: |
| 20 | compatible: |
| 21 | oneOf: |
| 22 | - enum: |
| 23 | - qcom,sdm845-gpi-dma |
| 24 | - qcom,sm6350-gpi-dma |
| 25 | - items: |
| 26 | - enum: |
| 27 | - qcom,qcm2290-gpi-dma |
| 28 | - qcom,qdu1000-gpi-dma |
| 29 | - qcom,sc7280-gpi-dma |
| 30 | - qcom,sm6115-gpi-dma |
| 31 | - qcom,sm6375-gpi-dma |
| 32 | - qcom,sm8350-gpi-dma |
| 33 | - qcom,sm8450-gpi-dma |
| 34 | - qcom,sm8550-gpi-dma |
| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 35 | - qcom,sm8650-gpi-dma |
| 36 | - qcom,x1e80100-gpi-dma |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 37 | - const: qcom,sm6350-gpi-dma |
| 38 | - items: |
| 39 | - enum: |
| 40 | - qcom,sdm670-gpi-dma |
| 41 | - qcom,sm6125-gpi-dma |
| 42 | - qcom,sm8150-gpi-dma |
| 43 | - qcom,sm8250-gpi-dma |
| 44 | - const: qcom,sdm845-gpi-dma |
| 45 | |
| 46 | reg: |
| 47 | maxItems: 1 |
| 48 | |
| 49 | interrupts: |
| 50 | description: |
| 51 | Interrupt lines for each GPI instance |
| 52 | minItems: 1 |
| 53 | maxItems: 13 |
| 54 | |
| 55 | "#dma-cells": |
| 56 | const: 3 |
| 57 | description: > |
| 58 | DMA clients must use the format described in dma.txt, giving a phandle |
| 59 | to the DMA controller plus the following 3 integer cells: |
| 60 | - channel: if set to 0xffffffff, any available channel will be allocated |
| 61 | for the client. Otherwise, the exact channel specified will be used. |
| 62 | - seid: serial id of the client as defined in the SoC documentation. |
| 63 | - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h |
| 64 | |
| 65 | iommus: |
| 66 | maxItems: 1 |
| 67 | |
| 68 | dma-channels: |
| 69 | maximum: 31 |
| 70 | |
| 71 | dma-channel-mask: |
| 72 | maxItems: 1 |
| 73 | |
| 74 | dma-coherent: true |
| 75 | |
| 76 | required: |
| 77 | - compatible |
| 78 | - reg |
| 79 | - interrupts |
| 80 | - "#dma-cells" |
| 81 | - iommus |
| 82 | - dma-channels |
| 83 | - dma-channel-mask |
| 84 | |
| 85 | additionalProperties: false |
| 86 | |
| 87 | examples: |
| 88 | - | |
| 89 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 90 | #include <dt-bindings/dma/qcom-gpi.h> |
| 91 | gpi_dma0: dma-controller@800000 { |
| 92 | compatible = "qcom,sdm845-gpi-dma"; |
| 93 | #dma-cells = <3>; |
| 94 | reg = <0x00800000 0x60000>; |
| 95 | iommus = <&apps_smmu 0x0016 0x0>; |
| 96 | dma-channels = <13>; |
| 97 | dma-channel-mask = <0xfa>; |
| 98 | interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, |
| 99 | <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| 100 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, |
| 101 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
| 102 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, |
| 103 | <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| 104 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
| 105 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| 106 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, |
| 107 | <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| 108 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| 109 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| 110 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; |
| 111 | }; |
| 112 | |
| 113 | ... |