| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: MediaTek AUDSYS controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Eugen Hristev <eugen.hristev@collabora.com> |
| 11 | |
| 12 | description: |
| 13 | The MediaTek AUDSYS controller provides various clocks to the system. |
| 14 | |
| 15 | properties: |
| 16 | compatible: |
| 17 | oneOf: |
| 18 | - items: |
| 19 | - enum: |
| 20 | - mediatek,mt2701-audsys |
| 21 | - mediatek,mt6765-audsys |
| 22 | - mediatek,mt6779-audsys |
| 23 | - mediatek,mt7622-audsys |
| 24 | - mediatek,mt8167-audsys |
| 25 | - mediatek,mt8173-audsys |
| 26 | - mediatek,mt8183-audsys |
| 27 | - mediatek,mt8186-audsys |
| 28 | - mediatek,mt8192-audsys |
| 29 | - mediatek,mt8516-audsys |
| 30 | - const: syscon |
| 31 | - items: |
| 32 | # Special case for mt7623 for backward compatibility |
| 33 | - const: mediatek,mt7623-audsys |
| 34 | - const: mediatek,mt2701-audsys |
| 35 | - const: syscon |
| 36 | |
| 37 | reg: |
| 38 | maxItems: 1 |
| 39 | |
| 40 | '#clock-cells': |
| 41 | const: 1 |
| 42 | |
| 43 | audio-controller: |
| 44 | $ref: /schemas/sound/mediatek,mt2701-audio.yaml# |
| 45 | type: object |
| 46 | |
| 47 | required: |
| 48 | - compatible |
| 49 | - '#clock-cells' |
| 50 | |
| 51 | additionalProperties: false |
| 52 | |
| 53 | examples: |
| 54 | - | |
| 55 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 56 | #include <dt-bindings/interrupt-controller/irq.h> |
| 57 | #include <dt-bindings/power/mt2701-power.h> |
| 58 | #include <dt-bindings/clock/mt2701-clk.h> |
| 59 | soc { |
| 60 | #address-cells = <2>; |
| 61 | #size-cells = <2>; |
| 62 | audsys: clock-controller@11220000 { |
| 63 | compatible = "mediatek,mt7622-audsys", "syscon"; |
| 64 | reg = <0 0x11220000 0 0x2000>; |
| 65 | #clock-cells = <1>; |
| 66 | |
| 67 | afe: audio-controller { |
| 68 | compatible = "mediatek,mt2701-audio"; |
| 69 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, |
| 70 | <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; |
| 71 | interrupt-names = "afe", "asys"; |
| 72 | power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; |
| 73 | |
| 74 | clocks = <&infracfg CLK_INFRA_AUDIO>, |
| 75 | <&topckgen CLK_TOP_AUD_MUX1_SEL>, |
| 76 | <&topckgen CLK_TOP_AUD_MUX2_SEL>, |
| 77 | <&topckgen CLK_TOP_AUD_48K_TIMING>, |
| 78 | <&topckgen CLK_TOP_AUD_44K_TIMING>, |
| 79 | <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, |
| 80 | <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, |
| 81 | <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, |
| 82 | <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, |
| 83 | <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, |
| 84 | <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, |
| 85 | <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, |
| 86 | <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, |
| 87 | <&topckgen CLK_TOP_AUD_I2S1_MCLK>, |
| 88 | <&topckgen CLK_TOP_AUD_I2S2_MCLK>, |
| 89 | <&topckgen CLK_TOP_AUD_I2S3_MCLK>, |
| 90 | <&topckgen CLK_TOP_AUD_I2S4_MCLK>, |
| 91 | <&audsys CLK_AUD_I2SO1>, |
| 92 | <&audsys CLK_AUD_I2SO2>, |
| 93 | <&audsys CLK_AUD_I2SO3>, |
| 94 | <&audsys CLK_AUD_I2SO4>, |
| 95 | <&audsys CLK_AUD_I2SIN1>, |
| 96 | <&audsys CLK_AUD_I2SIN2>, |
| 97 | <&audsys CLK_AUD_I2SIN3>, |
| 98 | <&audsys CLK_AUD_I2SIN4>, |
| 99 | <&audsys CLK_AUD_ASRCO1>, |
| 100 | <&audsys CLK_AUD_ASRCO2>, |
| 101 | <&audsys CLK_AUD_ASRCO3>, |
| 102 | <&audsys CLK_AUD_ASRCO4>, |
| 103 | <&audsys CLK_AUD_AFE>, |
| 104 | <&audsys CLK_AUD_AFE_CONN>, |
| 105 | <&audsys CLK_AUD_A1SYS>, |
| 106 | <&audsys CLK_AUD_A2SYS>, |
| 107 | <&audsys CLK_AUD_AFE_MRGIF>; |
| 108 | |
| 109 | clock-names = "infra_sys_audio_clk", |
| 110 | "top_audio_mux1_sel", |
| 111 | "top_audio_mux2_sel", |
| 112 | "top_audio_a1sys_hp", |
| 113 | "top_audio_a2sys_hp", |
| 114 | "i2s0_src_sel", |
| 115 | "i2s1_src_sel", |
| 116 | "i2s2_src_sel", |
| 117 | "i2s3_src_sel", |
| 118 | "i2s0_src_div", |
| 119 | "i2s1_src_div", |
| 120 | "i2s2_src_div", |
| 121 | "i2s3_src_div", |
| 122 | "i2s0_mclk_en", |
| 123 | "i2s1_mclk_en", |
| 124 | "i2s2_mclk_en", |
| 125 | "i2s3_mclk_en", |
| 126 | "i2so0_hop_ck", |
| 127 | "i2so1_hop_ck", |
| 128 | "i2so2_hop_ck", |
| 129 | "i2so3_hop_ck", |
| 130 | "i2si0_hop_ck", |
| 131 | "i2si1_hop_ck", |
| 132 | "i2si2_hop_ck", |
| 133 | "i2si3_hop_ck", |
| 134 | "asrc0_out_ck", |
| 135 | "asrc1_out_ck", |
| 136 | "asrc2_out_ck", |
| 137 | "asrc3_out_ck", |
| 138 | "audio_afe_pd", |
| 139 | "audio_afe_conn_pd", |
| 140 | "audio_a1sys_pd", |
| 141 | "audio_a2sys_pd", |
| 142 | "audio_mrgif_pd"; |
| 143 | |
| 144 | assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, |
| 145 | <&topckgen CLK_TOP_AUD_MUX2_SEL>, |
| 146 | <&topckgen CLK_TOP_AUD_MUX1_DIV>, |
| 147 | <&topckgen CLK_TOP_AUD_MUX2_DIV>; |
| 148 | assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, |
| 149 | <&topckgen CLK_TOP_AUD2PLL_90M>; |
| 150 | assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; |
| 151 | }; |
| 152 | }; |
| 153 | }; |