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git01.mediatek.com / filogic / uboot / a51226129111e6334120bd3c0d18fcd02419e735 / . / board / freescale / ls1046ardb / eth.c
blob: 9a07609820c661e12bcf2862ecdfdd4a58c764bc [file] [log] [blame]
Mingkai Hud2396512016-09-07 18:47:28 +0800[diff] [blame]1/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#include <common.h>
7#include <asm/io.h>
8#include <netdev.h>
9#include <fm_eth.h>
10#include <fsl_dtsec.h>
11#include <fsl_mdio.h>
12#include <malloc.h>
13
14#include "../common/fman.h"
15
16int board_eth_init(bd_t *bis)
17{
18#ifdef CONFIG_FMAN_ENET
19 int i;
20 struct memac_mdio_info dtsec_mdio_info;
21 struct memac_mdio_info tgec_mdio_info;
22 struct mii_dev *dev;
23 u32 srds_s1;
24 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
25
26 srds_s1 = in_be32(&gur->rcwsr[4]) &
27 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
28 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
29
30 dtsec_mdio_info.regs =
31 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
32
33 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
34
35 /* Register the 1G MDIO bus */
36 fm_memac_mdio_init(bis, &dtsec_mdio_info);
37
38 tgec_mdio_info.regs =
39 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
40 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
41
42 /* Register the 10G MDIO bus */
43 fm_memac_mdio_init(bis, &tgec_mdio_info);
44
45 /* Set the two on-board RGMII PHY address */
46 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
47 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
48
49 /* Set the two on-board SGMII PHY address */
50 fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
51 fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
52
53 /* Set the on-board AQ PHY address */
54 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
55
56 switch (srds_s1) {
57 case 0x1133:
58 break;
59 default:
60 printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
61 srds_s1);
62 break;
63 }
64
65 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
66 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
67 fm_info_set_mdio(i, dev);
68
69 /* XFI on lane A, MAC 9 */
70 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
71 fm_info_set_mdio(FM1_10GEC1, dev);
72
73 cpu_eth_init(bis);
74#endif
75
76 return pci_eth_init(bis);
77}
Prabhakar Kushwahaa5122612017-11-23 16:51:48 +0530[diff] [blame^]78
79#ifdef CONFIG_FMAN_ENET
80int fdt_update_ethernet_dt(void *blob)
81{
82 u32 srds_s1;
83 int i, prop;
84 int offset, nodeoff;
85 const char *path;
86 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
87
88 srds_s1 = in_be32(&gur->rcwsr[4]) &
89 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
90 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
91
92 /* Cycle through all aliases */
93 for (prop = 0; ; prop++) {
94 const char *name;
95
96 /* FDT might have been edited, recompute the offset */
97 offset = fdt_first_property_offset(blob,
98 fdt_path_offset(blob,
99 "/aliases")
100 );
101 /* Select property number 'prop' */
102 for (i = 0; i < prop; i++)
103 offset = fdt_next_property_offset(blob, offset);
104
105 if (offset < 0)
106 break;
107
108 path = fdt_getprop_by_offset(blob, offset, &name, NULL);
109 nodeoff = fdt_path_offset(blob, path);
110
111 switch (srds_s1) {
112 case 0x1133:
113 if (!strcmp(name, "ethernet0"))
114 fdt_status_disabled(blob, nodeoff);
115
116 if (!strcmp(name, "ethernet1"))
117 fdt_status_disabled(blob, nodeoff);
118 break;
119 default:
120 printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n",
121 __func__, srds_s1);
122 break;
123 }
124 }
125
126 return 0;
127}
128#endif