blob: d754f9f9040a82195428117a3de0b4b0a809793f [file] [log] [blame]
Michal Simeka335bd22016-04-07 16:00:11 +02001/*
2 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
3 *
4 * (C) Copyright 2015, Xilinx, Inc.
5 *
6 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
7 * Michal Simek <michal.simek@xilinx.com>
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12/dts-v1/;
13
14#include "zynqmp.dtsi"
15#include "zynqmp-clk.dtsi"
16/ {
17 model = "ZynqMP zc1751-xm019-dc5 RevA";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
19
20 aliases {
21 ethernet0 = &gem1;
22 gpio0 = &gpio;
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 mmc0 = &sdhci0;
26 serial0 = &uart0;
27 serial1 = &uart1;
28 };
29
30 chosen {
31 bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
32 stdout-path = "serial0:115200n8";
33 };
34
35 memory {
36 device_type = "memory";
37 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
38 };
39};
40
41/* fpd_dma clk 667MHz, lpd_dma 500MHz */
42&fpd_dma_chan1 {
43 status = "okay";
44 xlnx,include-sg; /* for testing purpose */
45 xlnx,overfetch; /* for testing purpose */
46 xlnx,ratectrl = <0>; /* for testing purpose */
47 xlnx,src-issue = <31>;
48};
49
50&fpd_dma_chan2 {
51 status = "okay";
52 xlnx,ratectrl = <100>; /* for testing purpose */
53 xlnx,src-issue = <4>; /* for testing purpose */
54};
55
56&fpd_dma_chan3 {
57 status = "okay";
58};
59
60&fpd_dma_chan4 {
61 status = "okay";
62 xlnx,include-sg; /* for testing purpose */
63};
64
65&fpd_dma_chan5 {
66 status = "okay";
67};
68
69&fpd_dma_chan6 {
70 status = "okay";
71 xlnx,include-sg; /* for testing purpose */
72};
73
74&fpd_dma_chan7 {
75 status = "okay";
76};
77
78&fpd_dma_chan8 {
79 status = "okay";
80 xlnx,include-sg; /* for testing purpose */
81};
82
83&gem1 {
84 status = "okay";
85 local-mac-address = [00 0a 35 00 02 90];
86 phy-handle = <&phy0>;
87 phy-mode = "rgmii-id";
88 phy0: phy@0 {
89 reg = <0>;
90 };
91};
92
93&gpio {
94 status = "okay";
95};
96
97/* FIXME: Add device */
98&i2c0 {
99 status = "okay";
100};
101
102/* FIXME: Add device */
103&i2c1 {
104 status = "okay";
105};
106
107&sdhci0 {
108 status = "okay";
109};
110
111&uart0 {
112 status = "okay";
113};
114
115&uart1 {
116 status = "okay";
117};
118
119&watchdog0 {
120 status = "okay";
121};