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Stelian Pop61e69d72008-05-08 20:52:22 +02001/*
2 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Pop61e69d72008-05-08 20:52:22 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * Configuation settings for the AT91SAM9261EK board.
7 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Stelian Pop61e69d72008-05-08 20:52:22 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/* ARM asynchronous clock */
Xu, Hong0a614942011-07-31 22:49:00 +000015#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Achim Ehrlich443873d2010-02-24 10:29:16 +010016#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Stelian Pop61e69d72008-05-08 20:52:22 +020017
Xu, Hong0a614942011-07-31 22:49:00 +000018#ifdef CONFIG_AT91SAM9G10
19#define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/
Sedji Gaouaou97a031b2009-06-25 17:04:15 +020020#else
Xu, Hong0a614942011-07-31 22:49:00 +000021#define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/
Sedji Gaouaou97a031b2009-06-25 17:04:15 +020022#endif
Xu, Hong0a614942011-07-31 22:49:00 +000023
24#include <asm/hardware.h>
25
Xu, Hong0a614942011-07-31 22:49:00 +000026#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
27#define CONFIG_SETUP_MEMORY_TAGS
28#define CONFIG_INITRD_TAG
Stelian Pop61e69d72008-05-08 20:52:22 +020029
30#define CONFIG_SKIP_LOWLEVEL_INIT
Stelian Pop61e69d72008-05-08 20:52:22 +020031
Xu, Hong0a614942011-07-31 22:49:00 +000032#define CONFIG_ATMEL_LEGACY
33#define CONFIG_SYS_TEXT_BASE 0x21f00000
34
Stelian Pop61e69d72008-05-08 20:52:22 +020035/*
36 * Hardware drivers
37 */
Xu, Hong0a614942011-07-31 22:49:00 +000038
39/* gpio */
40#define CONFIG_AT91_GPIO
41#define CONFIG_AT91_GPIO_PULLUP 1
42
43/* serial console */
44#define CONFIG_ATMEL_USART
45#define CONFIG_USART_BASE ATMEL_BASE_DBGU
46#define CONFIG_USART_ID ATMEL_ID_SYS
Stelian Pop61e69d72008-05-08 20:52:22 +020047
Stelian Pop905ed222008-05-08 14:52:30 +020048/* LCD */
Stelian Pop905ed222008-05-08 14:52:30 +020049#define LCD_BPP LCD_COLOR8
Xu, Hong0a614942011-07-31 22:49:00 +000050#define CONFIG_LCD_LOGO
Stelian Pop905ed222008-05-08 14:52:30 +020051#undef LCD_TEST_PATTERN
Xu, Hong0a614942011-07-31 22:49:00 +000052#define CONFIG_LCD_INFO
53#define CONFIG_LCD_INFO_BELOW_LOGO
54#define CONFIG_SYS_WHITE_ON_BLACK
55#define CONFIG_ATMEL_LCD
Sedji Gaouaou97a031b2009-06-25 17:04:15 +020056#ifdef CONFIG_AT91SAM9261EK
Xu, Hong0a614942011-07-31 22:49:00 +000057#define CONFIG_ATMEL_LCD_BGR555
Sedji Gaouaou97a031b2009-06-25 17:04:15 +020058#endif
Xu, Hong0a614942011-07-31 22:49:00 +000059
Jean-Christophe PLAGNIOL-VILLARD476d10e2009-03-21 21:08:00 +010060/* LED */
61#define CONFIG_AT91_LED
62#define CONFIG_RED_LED AT91_PIN_PA23 /* this is the power led */
63#define CONFIG_GREEN_LED AT91_PIN_PA13 /* this is the user1 led */
64#define CONFIG_YELLOW_LED AT91_PIN_PA14 /* this is the user2 led */
65
Stelian Pop61e69d72008-05-08 20:52:22 +020066
Stelian Pop61e69d72008-05-08 20:52:22 +020067/*
68 * BOOTP options
69 */
Xu, Hong0a614942011-07-31 22:49:00 +000070#define CONFIG_BOOTP_BOOTFILESIZE
71#define CONFIG_BOOTP_BOOTPATH
72#define CONFIG_BOOTP_GATEWAY
73#define CONFIG_BOOTP_HOSTNAME
Stelian Pop61e69d72008-05-08 20:52:22 +020074
75/*
76 * Command line configuration.
77 */
Xu, Hong0a614942011-07-31 22:49:00 +000078#define CONFIG_CMD_NAND
Stelian Pop61e69d72008-05-08 20:52:22 +020079
80/* SDRAM */
81#define CONFIG_NR_DRAM_BANKS 1
Xu, Hong0a614942011-07-31 22:49:00 +000082#define CONFIG_SYS_SDRAM_BASE 0x20000000
83#define CONFIG_SYS_SDRAM_SIZE 0x04000000
84#define CONFIG_SYS_INIT_SP_ADDR \
85 (ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
Stelian Pop61e69d72008-05-08 20:52:22 +020086
87/* DataFlash */
Jean-Christophe PLAGNIOL-VILLARDe5437ac2009-03-27 23:26:44 +010088#define CONFIG_ATMEL_DATAFLASH_SPI
Xu, Hong0a614942011-07-31 22:49:00 +000089#define CONFIG_HAS_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
91#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
92#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
Xu, Hong0a614942011-07-31 22:49:00 +000093#define AT91_SPI_CLK 15000000
94#define DATAFLASH_TCSS (0x1a << 16)
95#define DATAFLASH_TCHS (0x1 << 24)
Stelian Pop61e69d72008-05-08 20:52:22 +020096
97/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +010098#ifdef CONFIG_CMD_NAND
99#define CONFIG_NAND_ATMEL
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_MAX_NAND_DEVICE 1
101#define CONFIG_SYS_NAND_BASE 0x40000000
Xu, Hong0a614942011-07-31 22:49:00 +0000102#define CONFIG_SYS_NAND_DBW_8
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100103/* our ALE is AD22 */
104#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
105/* our CLE is AD21 */
106#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
107#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
108#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
Wolfgang Denk1f797742009-07-18 21:52:24 +0200109
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100110#endif
Stelian Pop61e69d72008-05-08 20:52:22 +0200111
Stelian Pop61e69d72008-05-08 20:52:22 +0200112/* Ethernet */
Xu, Hong0a614942011-07-31 22:49:00 +0000113#define CONFIG_DRIVER_DM9000
Stelian Pop61e69d72008-05-08 20:52:22 +0200114#define CONFIG_DM9000_BASE 0x30000000
115#define DM9000_IO CONFIG_DM9000_BASE
116#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
Xu, Hong0a614942011-07-31 22:49:00 +0000117#define CONFIG_DM9000_USE_16BIT
118#define CONFIG_DM9000_NO_SROM
Stelian Pop61e69d72008-05-08 20:52:22 +0200119#define CONFIG_NET_RETRY_COUNT 20
Xu, Hong0a614942011-07-31 22:49:00 +0000120#define CONFIG_RESET_PHY_R
Stelian Pop61e69d72008-05-08 20:52:22 +0200121
122/* USB */
Jean-Christophe PLAGNIOL-VILLARDd42643f2009-03-27 23:26:44 +0100123#define CONFIG_USB_ATMEL
Bo Shen4a985df2013-10-21 16:14:00 +0800124#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Xu, Hong0a614942011-07-31 22:49:00 +0000125#define CONFIG_USB_OHCI_NEW
Xu, Hong0a614942011-07-31 22:49:00 +0000126#define CONFIG_SYS_USB_OHCI_CPU_INIT
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
Sedji Gaouaou97a031b2009-06-25 17:04:15 +0200128#ifdef CONFIG_AT91SAM9G10EK
129#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10"
130#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
Sedji Gaouaou97a031b2009-06-25 17:04:15 +0200132#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Stelian Pop61e69d72008-05-08 20:52:22 +0200134
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Pop61e69d72008-05-08 20:52:22 +0200136
Xu, Hong0a614942011-07-31 22:49:00 +0000137#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Pop61e69d72008-05-08 20:52:22 +0200139
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200140#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
Stelian Pop61e69d72008-05-08 20:52:22 +0200141
142/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Xu, Hong0a614942011-07-31 22:49:00 +0000143#define CONFIG_ENV_IS_IN_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
Nicolas Ferre09e10902008-12-06 13:11:14 +0100145#define CONFIG_ENV_OFFSET 0x4200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200147#define CONFIG_ENV_SIZE 0x4200
Alexandre Belloni9ef19ba2012-07-02 04:26:58 +0000148#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
Stelian Pop61e69d72008-05-08 20:52:22 +0200149#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
150 "root=/dev/mtdblock0 " \
Albin Tonnerreeaa6db22009-07-22 18:30:03 +0200151 "mtdparts=atmel_nand:-(root) " \
Stelian Pop61e69d72008-05-08 20:52:22 +0200152 "rw rootfstype=jffs2"
153
Nicolas Ferre09e10902008-12-06 13:11:14 +0100154#elif CONFIG_SYS_USE_DATAFLASH_CS3
155
156/* bootstrap + u-boot + env + linux in dataflash on CS3 */
Xu, Hong0a614942011-07-31 22:49:00 +0000157#define CONFIG_ENV_IS_IN_DATAFLASH
Nicolas Ferre09e10902008-12-06 13:11:14 +0100158#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400)
159#define CONFIG_ENV_OFFSET 0x4200
160#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
161#define CONFIG_ENV_SIZE 0x4200
Alexandre Belloni9ef19ba2012-07-02 04:26:58 +0000162#define CONFIG_BOOTCOMMAND "cp.b 0xD0084000 0x22000000 0x210000; bootm"
Nicolas Ferre09e10902008-12-06 13:11:14 +0100163#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
164 "root=/dev/mtdblock0 " \
Albin Tonnerreeaa6db22009-07-22 18:30:03 +0200165 "mtdparts=atmel_nand:-(root) " \
Nicolas Ferre09e10902008-12-06 13:11:14 +0100166 "rw rootfstype=jffs2"
167
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200168#else /* CONFIG_SYS_USE_NANDFLASH */
Stelian Pop61e69d72008-05-08 20:52:22 +0200169
170/* bootstrap + u-boot + env + linux in nandflash */
Xu, Hong0a614942011-07-31 22:49:00 +0000171#define CONFIG_ENV_IS_IN_NAND
Bo Shena8fd0632013-02-20 00:16:25 +0000172#define CONFIG_ENV_OFFSET 0xc0000
173#define CONFIG_ENV_OFFSET_REDUND 0x100000
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200174#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
Bo Shena8fd0632013-02-20 00:16:25 +0000175#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
176#define CONFIG_BOOTARGS \
177 "console=ttyS0,115200 earlyprintk " \
178 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
179 "256k(env),256k(env_redundant),256k(spare)," \
180 "512k(dtb),6M(kernel)ro,-(rootfs) " \
181 "root=/dev/mtdblock7 rw rootfstype=jffs2"
Stelian Pop61e69d72008-05-08 20:52:22 +0200182#endif
183
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_CBSIZE 256
185#define CONFIG_SYS_MAXARGS 16
Xu, Hong0a614942011-07-31 22:49:00 +0000186#define CONFIG_SYS_LONGHELP
187#define CONFIG_CMDLINE_EDITING
Alexandre Belloni9ef19ba2012-07-02 04:26:58 +0000188#define CONFIG_AUTO_COMPLETE
Stelian Pop61e69d72008-05-08 20:52:22 +0200189
Stelian Pop61e69d72008-05-08 20:52:22 +0200190/*
191 * Size of malloc() pool
192 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Stelian Pop61e69d72008-05-08 20:52:22 +0200194
Stelian Pop61e69d72008-05-08 20:52:22 +0200195#endif