TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
| 3 | * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 6 | */ |
| 7 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 8 | #include <asm-offsets.h> |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 9 | #include <config.h> |
| 10 | #include "version.h" |
TsiChung Liew | 0ee47d4 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 11 | #include <asm/cache.h> |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 12 | |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 13 | #define _START _start |
| 14 | #define _FAULT _fault |
| 15 | |
| 16 | #define SAVE_ALL \ |
| 17 | move.w #0x2700,%sr; /* disable intrs */ \ |
| 18 | subl #60,%sp; /* space for 15 regs */ \ |
| 19 | moveml %d0-%d7/%a0-%a6,%sp@; |
| 20 | |
| 21 | #define RESTORE_ALL \ |
| 22 | moveml %sp@,%d0-%d7/%a0-%a6; \ |
| 23 | addl #60,%sp; /* space for 15 regs */ \ |
| 24 | rte; |
| 25 | |
| 26 | .text |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 27 | |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 28 | /* |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 29 | * Vector table. This is used for initial platform startup. |
| 30 | * These vectors are to catch any un-intended traps. |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 31 | */ |
| 32 | _vectors: |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 33 | INITSP: .long 0x00000000 /* Initial SP */ |
| 34 | INITPC: .long _START /* Initial PC */ |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 35 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 36 | vector02_0F: |
| 37 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 38 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 39 | |
| 40 | /* Reserved */ |
| 41 | vector10_17: |
| 42 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 43 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 44 | vector18_1F: |
| 45 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 46 | |
| 47 | /* TRAP #0 - #15 */ |
| 48 | vector20_2F: |
| 49 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 50 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 51 | |
| 52 | /* Reserved */ |
| 53 | vector30_3F: |
| 54 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 55 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 56 | |
| 57 | vector64_127: |
| 58 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 59 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 60 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 61 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 62 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 63 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 64 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 65 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 66 | |
| 67 | vector128_191: |
| 68 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 69 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 70 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 71 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 72 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 73 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 74 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 75 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 76 | |
| 77 | vector192_255: |
| 78 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 79 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 80 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 81 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 82 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 83 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 84 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 85 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 86 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 87 | .text |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 88 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 89 | .globl _start |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 90 | _start: |
| 91 | nop |
| 92 | nop |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 93 | move.w #0x2700,%sr /* Mask off Interrupt */ |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 94 | |
| 95 | /* Set vector base register at the beginning of the Flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 96 | move.l #CONFIG_SYS_FLASH_BASE, %d0 |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 97 | movec %d0, %VBR |
| 98 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 99 | move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 100 | movec %d0, %RAMBAR1 |
| 101 | |
| 102 | /* invalidate and disable cache */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 103 | move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */ |
| 104 | movec %d0, %CACR /* Invalidate cache */ |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 105 | nop |
| 106 | move.l #0, %d0 |
| 107 | movec %d0, %ACR0 |
| 108 | movec %d0, %ACR1 |
| 109 | |
| 110 | /* initialize general use internal ram */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 111 | move.l #0, %d0 |
| 112 | move.l #(ICACHE_STATUS), %a1 /* icache */ |
| 113 | move.l #(DCACHE_STATUS), %a2 /* icache */ |
| 114 | move.l %d0, (%a1) |
| 115 | move.l %d0, (%a2) |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 116 | |
angelo@sysam.it | ef9707c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 117 | /* put relocation table address to a5 */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 118 | move.l #__got_start, %a5 |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 119 | |
angelo@sysam.it | ef9707c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 120 | /* setup stack initially on top of internal static ram */ |
| 121 | move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp |
| 122 | |
| 123 | /* |
| 124 | * if configured, malloc_f arena will be reserved first, |
| 125 | * then (and always) gd struct space will be reserved |
| 126 | */ |
| 127 | move.l %sp, -(%sp) |
| 128 | move.l #board_init_f_alloc_reserve, %a1 |
| 129 | jsr (%a1) |
| 130 | |
| 131 | /* update stack and frame-pointers */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 132 | move.l %d0, %sp |
| 133 | move.l %sp, %fp |
angelo@sysam.it | ef9707c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 134 | |
| 135 | /* initialize reserved area */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 136 | move.l %d0, -(%sp) |
angelo@sysam.it | ef9707c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 137 | move.l #board_init_f_init_reserve, %a1 |
| 138 | jsr (%a1) |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 139 | |
angelo@sysam.it | b8cd132 | 2016-04-12 00:30:59 +0200 | [diff] [blame] | 140 | /* run low-level CPU init code (from flash) */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 141 | move.l #cpu_init_f, %a1 |
| 142 | jsr (%a1) |
| 143 | |
angelo@sysam.it | b8cd132 | 2016-04-12 00:30:59 +0200 | [diff] [blame] | 144 | /* run low-level board init code (from flash) */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 145 | clr.l %sp@- |
| 146 | move.l #board_init_f, %a1 |
| 147 | jsr (%a1) |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 148 | |
| 149 | /* board_init_f() does not return */ |
| 150 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 151 | /******************************************************************************/ |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 152 | |
| 153 | /* |
| 154 | * void relocate_code (addr_sp, gd, addr_moni) |
| 155 | * |
| 156 | * This "function" does not return, instead it continues in RAM |
| 157 | * after relocating the monitor code. |
| 158 | * |
| 159 | * r3 = dest |
| 160 | * r4 = src |
| 161 | * r5 = length in bytes |
| 162 | * r6 = cachelinesize |
| 163 | */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 164 | .globl relocate_code |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 165 | relocate_code: |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 166 | link.w %a6,#0 |
| 167 | move.l 8(%a6), %sp /* set new stack pointer */ |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 168 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 169 | move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ |
| 170 | move.l 16(%a6), %a0 /* Save copy of Destination Address */ |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 171 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 172 | move.l #CONFIG_SYS_MONITOR_BASE, %a1 |
| 173 | move.l #__init_end, %a2 |
| 174 | move.l %a0, %a3 |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 175 | |
| 176 | /* copy the code to RAM */ |
| 177 | 1: |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 178 | move.l (%a1)+, (%a3)+ |
| 179 | cmp.l %a1,%a2 |
| 180 | bgt.s 1b |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 181 | |
| 182 | /* |
| 183 | * We are done. Do not return, instead branch to second part of board |
| 184 | * initialization, now running from RAM. |
| 185 | */ |
| 186 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 187 | add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 188 | jmp (%a1) |
| 189 | |
| 190 | in_ram: |
| 191 | |
| 192 | clear_bss: |
| 193 | /* |
| 194 | * Now clear BSS segment |
| 195 | */ |
| 196 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 197 | add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 198 | move.l %a0, %d1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 199 | add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 200 | 6: |
| 201 | clr.l (%a1)+ |
| 202 | cmp.l %a1,%d1 |
| 203 | bgt.s 6b |
| 204 | |
| 205 | /* |
| 206 | * fix got table in RAM |
| 207 | */ |
| 208 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 209 | add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 210 | move.l %a1,%a5 /* * fix got pointer register a5 */ |
| 211 | |
| 212 | move.l %a0, %a2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 213 | add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 214 | |
| 215 | 7: |
| 216 | move.l (%a1),%d1 |
| 217 | sub.l #_start,%d1 |
| 218 | add.l %a0,%d1 |
| 219 | move.l %d1,(%a1)+ |
| 220 | cmp.l %a2, %a1 |
| 221 | bne 7b |
| 222 | |
| 223 | /* calculate relative jump to board_init_r in ram */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 224 | move.l %a0, %a1 |
| 225 | add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 226 | |
| 227 | /* set parameters for board_init_r */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 228 | move.l %a0,-(%sp) /* dest_addr */ |
| 229 | move.l %d0,-(%sp) /* gd */ |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 230 | jsr (%a1) |
| 231 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 232 | /******************************************************************************/ |
| 233 | |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 234 | /* exception code */ |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 235 | .globl _fault |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 236 | _fault: |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 237 | bra _fault |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 238 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 239 | .globl _exc_handler |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 240 | _exc_handler: |
| 241 | SAVE_ALL |
| 242 | movel %sp,%sp@- |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 243 | bsr exc_handler |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 244 | addql #4,%sp |
| 245 | RESTORE_ALL |
| 246 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 247 | .globl _int_handler |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 248 | _int_handler: |
| 249 | SAVE_ALL |
| 250 | movel %sp,%sp@- |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 251 | bsr int_handler |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 252 | addql #4,%sp |
| 253 | RESTORE_ALL |
| 254 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 255 | /******************************************************************************/ |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 256 | |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 257 | .globl version_string |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 258 | version_string: |
Angelo Dureghello | 65d5991 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 259 | .ascii U_BOOT_VERSION_STRING, "\0" |
| 260 | .align 4 |