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git01.mediatek.com / filogic / uboot / a4ad96edb2dce213dbb8aa4917bd967de67e4769 / . / arch / arm / mach-uniphier / clk / clk-pxs2.c
blob: 27fb2f44b4e3bed390cdd8a38c42ba58567f00f6 [file] [log] [blame]
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]1/*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
Masahiro Yamada85ab6072016-07-22 20:20:11 +0900[diff] [blame]7#include <linux/bitops.h>
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]8#include <linux/io.h>
Masahiro Yamadaefdf3402016-01-09 01:51:13 +0900[diff] [blame]9
10#include "../init.h"
11#include "../sc-regs.h"
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]12
Masahiro Yamada98905692016-03-30 20:17:02 +0900[diff] [blame]13void uniphier_pxs2_clk_init(void)
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]14{
15 u32 tmp;
16
17 /* deassert reset */
18 tmp = readl(SC_RSTCTRL);
Masahiro Yamada260eda22017-10-14 02:21:17 +0900[diff] [blame]19#ifdef CONFIG_USB_DWC3_UNIPHIER
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]20 tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
21#endif
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]22#ifdef CONFIG_NAND_DENALI
23 tmp |= SC_RSTCTRL_NRST_NAND;
24#endif
25 writel(tmp, SC_RSTCTRL);
26 readl(SC_RSTCTRL); /* dummy read */
27
Masahiro Yamada260eda22017-10-14 02:21:17 +0900[diff] [blame]28#ifdef CONFIG_USB_DWC3_UNIPHIER
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]29 tmp = readl(SC_RSTCTRL2);
30 tmp |= SC_RSTCTRL2_NRST_USB3B1;
31 writel(tmp, SC_RSTCTRL2);
32 readl(SC_RSTCTRL2); /* dummy read */
Masahiro Yamada85ab6072016-07-22 20:20:11 +0900[diff] [blame]33
34 tmp = readl(SC_RSTCTRL6);
35 tmp |= 0x37;
36 writel(tmp, SC_RSTCTRL6);
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]37#endif
38
Masahiro Yamada1c6a5e42016-03-30 20:17:42 +0900[diff] [blame]39 /* provide clocks */
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]40 tmp = readl(SC_CLKCTRL);
Masahiro Yamada260eda22017-10-14 02:21:17 +0900[diff] [blame]41#ifdef CONFIG_USB_DWC3_UNIPHIER
Masahiro Yamada85ab6072016-07-22 20:20:11 +0900[diff] [blame]42 tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]43 SC_CLKCTRL_CEN_GIO;
44#endif
Masahiro Yamada1fe65d32015-09-22 00:27:41 +0900[diff] [blame]45#ifdef CONFIG_NAND_DENALI
46 tmp |= SC_CLKCTRL_CEN_NAND;
47#endif
48 writel(tmp, SC_CLKCTRL);
49 readl(SC_CLKCTRL); /* dummy read */
50}