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Feng Kan33384d12008-07-08 22:48:07 -07001/*
2 * Configuration for AMCC 460SX Ref (redwood)
3 *
4 * (C) Copyright 2008
5 * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Feng Kan33384d12008-07-08 22:48:07 -07008 */
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*-----------------------------------------------------------------------
13 * High Level Configuration Options
14 *----------------------------------------------------------------------*/
Feng Kan33384d12008-07-08 22:48:07 -070015#define CONFIG_440 1 /* ... PPC460 family */
16#define CONFIG_460SX 1 /* ... PPC460 family */
17#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
18
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020019#define CONFIG_SYS_TEXT_BASE 0xfffb0000
20
Feng Kan33384d12008-07-08 22:48:07 -070021/*-----------------------------------------------------------------------
22 * Include common defines/options for all AMCC boards
23 *----------------------------------------------------------------------*/
24#define CONFIG_HOSTNAME redwood
25
26#include "amcc-common.h"
27
28#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
29
30/*-----------------------------------------------------------------------
31 * Base addresses -- Note these are effective addresses where the
32 * actual resources get mapped (not physical addresses)
33 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020035#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
Feng Kan33384d12008-07-08 22:48:07 -070036
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020037#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
Feng Kan33384d12008-07-08 22:48:07 -070038
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020039#define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
40#define CONFIG_SYS_PCIE0_MEMBASE 0x90000000 /* mapped PCIe memory */
41#define CONFIG_SYS_PCIE1_MEMBASE 0xa0000000 /* mapped PCIe memory */
42#define CONFIG_SYS_PCIE_MEMSIZE 0x01000000
Feng Kan33384d12008-07-08 22:48:07 -070043
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020044#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000
45#define CONFIG_SYS_PCIE1_XCFGBASE 0xb2000000
46#define CONFIG_SYS_PCIE2_XCFGBASE 0xb4000000
47#define CONFIG_SYS_PCIE0_CFGBASE 0xb6000000
48#define CONFIG_SYS_PCIE1_CFGBASE 0xb8000000
49#define CONFIG_SYS_PCIE2_CFGBASE 0xba000000
Feng Kan33384d12008-07-08 22:48:07 -070050
51/* PCIe mapped UTL registers */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020052#define CONFIG_SYS_PCIE0_REGBASE 0xd0000000
53#define CONFIG_SYS_PCIE1_REGBASE 0xd0010000
54#define CONFIG_SYS_PCIE2_REGBASE 0xd0020000
Feng Kan33384d12008-07-08 22:48:07 -070055
56/* System RAM mapped to PCI space */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
58#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
Feng Kan33384d12008-07-08 22:48:07 -070059#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
60
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_FPGA_BASE 0xe2000000 /* epld */
62#define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
Feng Kan33384d12008-07-08 22:48:07 -070063
Stefan Roese3ddce572010-09-20 16:05:31 +020064/*
65 * Serial Port
66 */
67#define CONFIG_CONS_INDEX 1 /* Use UART0 */
68
Feng Kan33384d12008-07-08 22:48:07 -070069/*-----------------------------------------------------------------------
70 * Initial RAM & stack pointer (placed in internal SRAM)
71 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072#define CONFIG_SYS_TEMP_STACK_OCM 1
73#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
74#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +020075#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Feng Kan33384d12008-07-08 22:48:07 -070076
Wolfgang Denk0191e472010-10-26 14:34:52 +020077#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidmanf969a682010-09-20 08:51:53 +020078#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Feng Kan33384d12008-07-08 22:48:07 -070079
80/*-----------------------------------------------------------------------
81 * DDR SDRAM
82 *----------------------------------------------------------------------*/
83#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
84#define CONFIG_DDR_ECC 1 /* with ECC support */
85
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086#define CONFIG_SYS_SPD_MAX_DIMMS 2
Feng Kan33384d12008-07-08 22:48:07 -070087
88/* SPD i2c spd addresses */
89#define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
Heiko Schocher9e25d762008-08-19 09:57:41 +020090#define IIC0_DIMM0_ADDR 0x53
91#define IIC0_DIMM1_ADDR 0x52
Feng Kan33384d12008-07-08 22:48:07 -070092
93/*-----------------------------------------------------------------------
94 * I2C
95 *----------------------------------------------------------------------*/
Dirk Eibach42b204f2013-04-25 02:40:01 +000096#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Feng Kan33384d12008-07-08 22:48:07 -070097
98#define IIC0_BOOTPROM_ADDR 0x50
99#define IIC0_ALT_BOOTPROM_ADDR 0x54
100
101/* Don't probe these addrs */
Dirk Eibach42b204f2013-04-25 02:40:01 +0000102#define CONFIG_SYS_I2C_NOPROBES { {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
Feng Kan33384d12008-07-08 22:48:07 -0700103
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
Feng Kan33384d12008-07-08 22:48:07 -0700105
106/*-----------------------------------------------------------------------
107 * Environment
108 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +0200109#undef CONFIG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200110#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200111#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
Feng Kan33384d12008-07-08 22:48:07 -0700112
113#define CONFIG_PREBOOT "echo;" \
114 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
115 "echo"
116
117#undef CONFIG_BOOTARGS
118
119#define CONFIG_EXTRA_ENV_SETTINGS \
Heiko Schocher9e25d762008-08-19 09:57:41 +0200120 CONFIG_AMCC_DEF_ENV \
121 CONFIG_AMCC_DEF_ENV_POWERPC \
122 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Heiko Schocher9e25d762008-08-19 09:57:41 +0200123 "kernel_addr=fc000000\0" \
124 "fdt_addr=fc1e0000\0" \
125 "ramdisk_addr=fc200000\0" \
Feng Kan33384d12008-07-08 22:48:07 -0700126 ""
127
128/*----------------------------------------------------------------------------+
129| Commands in addition to amcc-common.h
130+----------------------------------------------------------------------------*/
131#define CONFIG_CMD_SDRAM
132
133#define CONFIG_BOOTCOMMAND "run flash_self"
134
Feng Kan33384d12008-07-08 22:48:07 -0700135
136#define CONFIG_IBM_EMAC4_V4 1
Heiko Schocher9e25d762008-08-19 09:57:41 +0200137#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Feng Kan33384d12008-07-08 22:48:07 -0700138#define CONFIG_PHY_RESET_DELAY 1000
139#define CONFIG_M88E1141_PHY 1 /* Enable phy */
140#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
141
142#define CONFIG_HAS_ETH0
143#define CONFIG_HAS_ETH1
144#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
145#define CONFIG_PHY1_ADDR 1 /* PHY address, See schematics */
146
147#undef CONFIG_WATCHDOG /* watchdog disabled */
148
149/*-----------------------------------------------------------------------
150 * FLASH related
151 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Heiko Schocher9e25d762008-08-19 09:57:41 +0200153#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
Feng Kan33384d12008-07-08 22:48:07 -0700155
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200156#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
157#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
Feng Kan33384d12008-07-08 22:48:07 -0700158
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200159#undef CONFIG_SYS_FLASH_CHECKSUM
160#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
161#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Feng Kan33384d12008-07-08 22:48:07 -0700162
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200163#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200164#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
165#define CONFIG_ENV_ADDR 0xfffa0000
166#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment vars */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200167#endif /* CONFIG_ENV_IS_IN_FLASH */
Feng Kan33384d12008-07-08 22:48:07 -0700168
169/*---------------------------------------------------------------------------*/
170
171#endif /* __CONFIG_H */