| Aradhya Bhatia | 94024e9 | 2023-04-14 12:57:25 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Keystone3 Quality of service endpoint definitions |
| 4 | * Auto generated by K3 Resource Partitioning Tool |
| 5 | * |
| 6 | * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ |
| 7 | */ |
| 8 | |
| 9 | #define QOS_0 (0 << 0) |
| 10 | #define QOS_1 (1 << 0) |
| 11 | #define QOS_2 (2 << 0) |
| 12 | #define QOS_3 (3 << 0) |
| 13 | #define QOS_4 (4 << 0) |
| 14 | #define QOS_5 (5 << 0) |
| 15 | #define QOS_6 (6 << 0) |
| 16 | #define QOS_7 (7 << 0) |
| 17 | |
| 18 | #define ORDERID_0 (0 << 4) |
| 19 | #define ORDERID_1 (1 << 4) |
| 20 | #define ORDERID_2 (2 << 4) |
| 21 | #define ORDERID_3 (3 << 4) |
| 22 | #define ORDERID_4 (4 << 4) |
| 23 | #define ORDERID_5 (5 << 4) |
| 24 | #define ORDERID_6 (6 << 4) |
| 25 | #define ORDERID_7 (7 << 4) |
| 26 | #define ORDERID_8 (8 << 4) |
| 27 | #define ORDERID_9 (9 << 4) |
| 28 | #define ORDERID_10 (10 << 4) |
| 29 | #define ORDERID_11 (11 << 4) |
| 30 | #define ORDERID_12 (12 << 4) |
| 31 | #define ORDERID_13 (13 << 4) |
| 32 | #define ORDERID_14 (14 << 4) |
| 33 | #define ORDERID_15 (15 << 4) |
| 34 | |
| 35 | #define ASEL_0 (0 << 8) |
| 36 | #define ASEL_1 (1 << 8) |
| 37 | #define ASEL_2 (2 << 8) |
| 38 | #define ASEL_3 (3 << 8) |
| 39 | #define ASEL_4 (4 << 8) |
| 40 | #define ASEL_5 (5 << 8) |
| 41 | #define ASEL_6 (6 << 8) |
| 42 | #define ASEL_7 (7 << 8) |
| 43 | #define ASEL_8 (8 << 8) |
| 44 | #define ASEL_9 (9 << 8) |
| 45 | #define ASEL_10 (10 << 8) |
| 46 | #define ASEL_11 (11 << 8) |
| 47 | #define ASEL_12 (12 << 8) |
| 48 | #define ASEL_13 (13 << 8) |
| 49 | #define ASEL_14 (14 << 8) |
| 50 | #define ASEL_15 (15 << 8) |
| 51 | |
| 52 | #define EPRIORITY_0 (0 << 12) |
| 53 | #define EPRIORITY_1 (1 << 12) |
| 54 | #define EPRIORITY_2 (2 << 12) |
| 55 | #define EPRIORITY_3 (3 << 12) |
| 56 | #define EPRIORITY_4 (4 << 12) |
| 57 | #define EPRIORITY_5 (5 << 12) |
| 58 | #define EPRIORITY_6 (6 << 12) |
| 59 | #define EPRIORITY_7 (7 << 12) |
| 60 | |
| 61 | #define VIRTID_0 (0 << 16) |
| 62 | #define VIRTID_1 (1 << 16) |
| 63 | #define VIRTID_2 (2 << 16) |
| 64 | #define VIRTID_3 (3 << 16) |
| 65 | #define VIRTID_4 (4 << 16) |
| 66 | #define VIRTID_5 (5 << 16) |
| 67 | #define VIRTID_6 (6 << 16) |
| 68 | #define VIRTID_7 (7 << 16) |
| 69 | #define VIRTID_8 (8 << 16) |
| 70 | #define VIRTID_9 (9 << 16) |
| 71 | #define VIRTID_10 (10 << 16) |
| 72 | #define VIRTID_11 (11 << 16) |
| 73 | #define VIRTID_12 (12 << 16) |
| 74 | #define VIRTID_13 (13 << 16) |
| 75 | #define VIRTID_14 (14 << 16) |
| 76 | #define VIRTID_15 (15 << 16) |
| 77 | |
| 78 | #define ATYPE_0 (0 << 28) |
| 79 | #define ATYPE_1 (1 << 28) |
| 80 | #define ATYPE_2 (2 << 28) |
| 81 | #define ATYPE_3 (3 << 28) |
| 82 | |
| 83 | #define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000 |
| 84 | #define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400 |
| 85 | #define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800 |
| 86 | #define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000 |
| 87 | #define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400 |
| 88 | #define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800 |
| 89 | #define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R 0x45D20400 |
| 90 | #define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W 0x45D20800 |
| 91 | #define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45D21800 |
| 92 | #define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45D21C00 |
| 93 | #define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM 0x45D22000 |
| 94 | #define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM 0x45D22400 |
| 95 | #define EMMCSD8SS_MAIN_0_EMMCSDSS_RD 0x45D22800 |
| 96 | #define EMMCSD8SS_MAIN_0_EMMCSDSS_WR 0x45D22C00 |
| 97 | #define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D23000 |
| 98 | #define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D23400 |
| 99 | #define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D23800 |
| 100 | #define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D23C00 |
| 101 | #define USB2SS_16FFC_MAIN_0_MSTW0 0x45D24000 |
| 102 | #define USB2SS_16FFC_MAIN_0_MSTR0 0x45D24400 |
| 103 | #define USB2SS_16FFC_MAIN_1_MSTR0 0x45D24800 |
| 104 | #define USB2SS_16FFC_MAIN_1_MSTW0 0x45D24C00 |
| 105 | #define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D25000 |
| 106 | #define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400 |
| 107 | #define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W 0x45D25800 |
| 108 | #define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R 0x45D25C00 |
| 109 | #define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45D26800 |
| 110 | #define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45D26C00 |
| 111 | #define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45D27000 |
| 112 | #define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45D27400 |
| 113 | #define SAM62A_C7XV_WRAP_MAIN_0_C7XV_SOC 0x45D27800 |
| 114 | #define SAM62A_VPAC_WRAP_MAIN_0_LDC0_M_MST 0x45D28000 |