blob: 6894298526efc58b6e1d91f806769cca52ccd906 [file] [log] [blame]
Simon Glassec1a30c2019-12-06 21:41:43 -07001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2017 Intel Corporation.
4 */
5
6#ifndef ASM_FAST_SPI_H
7#define ASM_FAST_SPI_H
8
9/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
10struct fast_spi_regs {
11 u32 bfp;
12 u32 hsfsts_ctl;
13 u32 faddr;
14 u32 dlock;
15
16 u32 fdata[0x10];
17
18 u32 fracc;
19 u32 freg[12];
20 u32 fpr[5];
21 u32 gpr0;
22 u32 spare2;
23 u32 sts_ctl;
24 u16 preop;
25 u16 optype;
26 u8 opmenu[8];
27
28 u32 spare3;
29 u32 fdoc;
30 u32 fdod;
31 u32 spare4;
32 u32 afc;
33 u32 vscc[2];
34 u32 ptinx;
35 u32 ptdata;
36};
37check_member(fast_spi_regs, ptdata, 0xd0);
38
39/* Bit definitions for BFPREG (0x00) register */
40#define SPIBAR_BFPREG_PRB_MASK 0x7fff
41#define SPIBAR_BFPREG_PRL_SHIFT 16
42#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT)
43
44/* PCI configuration registers */
45#define SPIBAR_BIOS_CONTROL 0xdc
46#define SPIBAR_BIOS_CONTROL_WPD BIT(0)
47#define SPIBAR_BIOS_CONTROL_LOCK_ENABLE BIT(1)
48#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE BIT(2)
49#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE BIT(3)
50#define SPIBAR_BIOS_CONTROL_EISS BIT(5)
51#define SPIBAR_BIOS_CONTROL_BILD BIT(7)
52
53/**
54 * fast_spi_get_bios_mmap() - Get memory map for SPI flash
55 *
56 * @pdev: PCI device to use (this is the Fast SPI device)
57 * @map_basep: Returns base memory address for mapped SPI
58 * @map_sizep: Returns size of mapped SPI
59 * @offsetp: Returns start offset of SPI flash where the map works
60 * correctly (offsets before this are not visible)
61 * @return 0 (always)
62 */
63int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep,
64 uint *offsetp);
65
66int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base);
67
68#endif /* ASM_FAST_SPI_H */