| Simon Glass | 398336e | 2019-02-16 20:25:01 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Support for Intel Application Digital Signal Processor |
| 4 | * |
| 5 | * Copyright 2019 Google LLC |
| 6 | * |
| 7 | * Modified from coreboot file of the same name |
| 8 | */ |
| 9 | |
| 10 | #ifndef __ASM_ARCH_BROADWELL_ADSP_H |
| 11 | #define __ASM_ARCH_BROADWELL_ADSP_H |
| 12 | |
| 13 | #define ADSP_PCI_IRQ 23 |
| 14 | #define ADSP_ACPI_IRQ 3 |
| 15 | #define ADSP_ACPI_IRQEN BIT(3) |
| 16 | |
| 17 | #define ADSP_SHIM_BASE_LPT 0xe7000 |
| 18 | #define ADSP_SHIM_BASE_WPT 0xfb000 |
| 19 | #define ADSP_SHIM_LTRC 0xe0 |
| 20 | #define ADSP_SHIM_LTRC_VALUE 0x3003 |
| 21 | #define ADSP_SHIM_IMC 0x28 |
| 22 | #define ADSP_SHIM_IPCD 0x40 |
| 23 | |
| 24 | #define ADSP_PCI_VDRTCTL0 0xa0 |
| 25 | #define ADSP_VDRTCTL0_D3PGD_LPT BIT(1) |
| 26 | #define ADSP_VDRTCTL0_D3PGD_WPT BIT(0) |
| 27 | #define ADSP_VDRTCTL0_D3SRAMPGD_LPT BIT(2) |
| 28 | #define ADSP_VDRTCTL0_D3SRAMPGD_WPT BIT(1) |
| 29 | #define ADSP_PCI_VDRTCTL1 0xa4 |
| 30 | #define ADSP_PCI_VDRTCTL2 0xa8 |
| 31 | #define ADSP_VDRTCTL2_VALUE 0x00000fff |
| 32 | |
| 33 | #define ADSP_IOBP_VDLDAT1 0xd7000624 |
| 34 | #define ADSP_VDLDAT1_VALUE 0x00040100 |
| 35 | #define ADSP_IOBP_VDLDAT2 0xd7000628 |
| 36 | #define ADSP_IOBP_ACPI_IRQ3 0xd9d8 |
| 37 | #define ADSP_IOBP_ACPI_IRQ3I 0xd8d9 |
| 38 | #define ADSP_IOBP_ACPI_IRQ4 0xdbda |
| 39 | #define ADSP_IOBP_PMCTL 0xd70001e0 |
| 40 | #define ADSP_PMCTL_VALUE 0x3f |
| 41 | #define ADSP_IOBP_PCICFGCTL 0xd7000500 |
| 42 | #define ADSP_PCICFGCTL_PCICD BIT(0) |
| 43 | #define ADSP_PCICFGCTL_ACPIIE BIT(1) |
| 44 | #define ADSP_PCICFGCTL_SPCBAD BIT(7) |
| 45 | |
| 46 | #endif /* __ASM_ARCH_BROADWELL_ADSP_H */ |