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git01.mediatek.com / filogic / uboot / a473057268d9e0b13ed7754f6fa9ab731fe4878c / . / arch / sandbox / dts / test.dts
blob: df9f1835c9e9ff387772e2ea58adedc37215dd01 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +0100[diff] [blame]3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
5
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]6/ {
7 model = "sandbox";
8 compatible = "sandbox";
9 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]10 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]11
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]12 aliases {
13 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]14 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]15 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]16 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]17 gpio1 = &gpio_a;
18 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100[diff] [blame]19 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]20 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]21 mmc0 = "/mmc0";
22 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]23 pci0 = &pci0;
24 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]25 pci2 = &pci2;
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]26 remoteproc1 = &rproc_1;
27 remoteproc2 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]28 rtc0 = &rtc_0;
29 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]30 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]31 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]32 testbus3 = "/some-bus";
33 testfdt0 = "/some-bus/c-test@0";
34 testfdt1 = "/some-bus/c-test@1";
35 testfdt3 = "/b-test";
36 testfdt5 = "/some-bus/c-test@5";
37 testfdt8 = "/a-test";
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +0200[diff] [blame]38 fdt-dummy0 = "/translation-test@8000/dev@0,0";
39 fdt-dummy1 = "/translation-test@8000/dev@1,100";
40 fdt-dummy2 = "/translation-test@8000/dev@2,200";
41 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]42 usb0 = &usb_0;
43 usb1 = &usb_1;
44 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]45 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]46 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]47 };
48
Simon Glassed96cde2018-12-10 10:37:33 -0700[diff] [blame]49 audio: audio-codec {
50 compatible = "sandbox,audio-codec";
51 #sound-dai-cells = <1>;
52 };
53
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]54 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600[diff] [blame]55 reg = <0 0>;
56 compatible = "google,cros-ec-sandbox";
57
58 /*
59 * This describes the flash memory within the EC. Note
60 * that the STM32L flash erases to 0, not 0xff.
61 */
62 flash {
63 image-pos = <0x08000000>;
64 size = <0x20000>;
65 erase-value = <0>;
66
67 /* Information for sandbox */
68 ro {
69 image-pos = <0>;
70 size = <0xf000>;
71 };
72 wp-ro {
73 image-pos = <0xf000>;
74 size = <0x1000>;
75 };
76 rw {
77 image-pos = <0x10000>;
78 size = <0x10000>;
79 };
80 };
81 };
82
Yannick Fertré9712c822019-10-07 15:29:05 +0200[diff] [blame]83 dsi_host: dsi_host {
84 compatible = "sandbox,dsi-host";
85 };
86
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]87 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]88 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]89 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]90 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]91 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]92 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100[diff] [blame]93 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
94 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]95 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100[diff] [blame]96 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
97 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
98 <&gpio_b 7 GPIO_IN 3 2 1>,
99 <&gpio_b 8 GPIO_OUT 3 2 1>,
100 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100[diff] [blame]101 test3-gpios =
102 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
103 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
104 <&gpio_c 2 GPIO_OUT>,
105 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
106 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
107 <&gpio_c 5 GPIO_IN>;
Simon Glass6df01f92018-12-10 10:37:37 -0700[diff] [blame]108 int-value = <1234>;
109 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200[diff] [blame]110 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200[diff] [blame]111 int-array = <5678 9123 4567>;
Simon Glass515dcff2020-02-06 09:55:00 -0700[diff] [blame]112 interrupts-extended = <&irq 3 0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]113 };
114
115 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]116 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]117 compatible = "not,compatible";
118 };
119
120 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]121 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]122 };
123
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]124 backlight: backlight {
125 compatible = "pwm-backlight";
126 enable-gpios = <&gpio_a 1>;
127 power-supply = <&ldo_1>;
128 pwms = <&pwm 0 1000>;
129 default-brightness-level = <5>;
130 brightness-levels = <0 16 32 64 128 170 202 234 255>;
131 };
132
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200[diff] [blame]133 bind-test {
134 bind-test-child1 {
135 compatible = "sandbox,phy";
136 #phy-cells = <1>;
137 };
138
139 bind-test-child2 {
140 compatible = "simple-bus";
141 };
142 };
143
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]144 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]145 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]146 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]147 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]148 ping-add = <3>;
149 };
150
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200[diff] [blame]151 phy_provider0: gen_phy@0 {
152 compatible = "sandbox,phy";
153 #phy-cells = <1>;
154 };
155
156 phy_provider1: gen_phy@1 {
157 compatible = "sandbox,phy";
158 #phy-cells = <0>;
159 broken;
160 };
161
162 gen_phy_user: gen_phy_user {
163 compatible = "simple-bus";
164 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
165 phy-names = "phy1", "phy2", "phy3";
166 };
167
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]168 some-bus {
169 #address-cells = <1>;
170 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]171 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]172 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]173 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]174 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]175 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]176 compatible = "denx,u-boot-fdt-test";
177 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]178 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]179 ping-add = <5>;
180 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]181 c-test@0 {
182 compatible = "denx,u-boot-fdt-test";
183 reg = <0>;
184 ping-expect = <6>;
185 ping-add = <6>;
186 };
187 c-test@1 {
188 compatible = "denx,u-boot-fdt-test";
189 reg = <1>;
190 ping-expect = <7>;
191 ping-add = <7>;
192 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]193 };
194
195 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]196 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]197 ping-expect = <6>;
198 ping-add = <6>;
199 compatible = "google,another-fdt-test";
200 };
201
202 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]203 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]204 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]205 ping-add = <6>;
206 compatible = "google,another-fdt-test";
207 };
208
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]209 f-test {
210 compatible = "denx,u-boot-fdt-test";
211 };
212
213 g-test {
214 compatible = "denx,u-boot-fdt-test";
215 };
216
Bin Mengd9d24782018-10-10 22:07:01 -0700[diff] [blame]217 h-test {
218 compatible = "denx,u-boot-fdt-test1";
219 };
220
Simon Glass204675c2019-12-29 21:19:25 -0700[diff] [blame]221 devres-test {
222 compatible = "denx,u-boot-devres-test";
223 };
224
Simon Glass2d67fdf2020-04-08 16:57:34 -0600[diff] [blame]225 acpi-test {
226 compatible = "denx,u-boot-acpi-test";
227 };
228
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200[diff] [blame]229 clocks {
230 clk_fixed: clk-fixed {
231 compatible = "fixed-clock";
232 #clock-cells = <0>;
233 clock-frequency = <1234>;
234 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000[diff] [blame]235
236 clk_fixed_factor: clk-fixed-factor {
237 compatible = "fixed-factor-clock";
238 #clock-cells = <0>;
239 clock-div = <3>;
240 clock-mult = <2>;
241 clocks = <&clk_fixed>;
242 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200[diff] [blame]243
244 osc {
245 compatible = "fixed-clock";
246 #clock-cells = <0>;
247 clock-frequency = <20000000>;
248 };
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]249 };
250
251 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]252 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]253 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200[diff] [blame]254 assigned-clocks = <&clk_sandbox 3>;
255 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600[diff] [blame]256 };
257
258 clk-test {
259 compatible = "sandbox,clk-test";
260 clocks = <&clk_fixed>,
261 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200[diff] [blame]262 <&clk_sandbox 0>,
263 <&clk_sandbox 3>,
264 <&clk_sandbox 2>;
265 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600[diff] [blame]266 };
267
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200[diff] [blame]268 ccf: clk-ccf {
269 compatible = "sandbox,clk-ccf";
270 };
271
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]272 eth@10002000 {
273 compatible = "sandbox,eth";
274 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]275 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]276 };
277
278 eth_5: eth@10003000 {
279 compatible = "sandbox,eth";
280 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]281 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]282 };
283
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]284 eth_3: sbe5 {
285 compatible = "sandbox,eth";
286 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]287 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700[diff] [blame]288 };
289
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]290 eth@10004000 {
291 compatible = "sandbox,eth";
292 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500[diff] [blame]293 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]294 };
295
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700[diff] [blame]296 firmware {
297 sandbox_firmware: sandbox-firmware {
298 compatible = "sandbox,firmware";
299 };
300 };
301
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100[diff] [blame]302 pinctrl-gpio {
303 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]304
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100[diff] [blame]305 gpio_a: base-gpios {
306 compatible = "sandbox,gpio";
307 gpio-controller;
308 #gpio-cells = <1>;
309 gpio-bank-name = "a";
310 sandbox,gpio-count = <20>;
311 };
312
313 gpio_b: extra-gpios {
314 compatible = "sandbox,gpio";
315 gpio-controller;
316 #gpio-cells = <5>;
317 gpio-bank-name = "b";
318 sandbox,gpio-count = <10>;
319 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]320
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100[diff] [blame]321 gpio_c: pinmux-gpios {
322 compatible = "sandbox,gpio";
323 gpio-controller;
324 #gpio-cells = <2>;
325 gpio-bank-name = "c";
326 sandbox,gpio-count = <10>;
327 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100[diff] [blame]328 };
329
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]330 i2c@0 {
331 #address-cells = <1>;
332 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]333 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]334 compatible = "sandbox,i2c";
335 clock-frequency = <100000>;
336 eeprom@2c {
337 reg = <0x2c>;
338 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]339 sandbox,emul = <&emul_eeprom>;
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]340 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]341
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]342 rtc_0: rtc@43 {
343 reg = <0x43>;
344 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]345 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]346 };
347
348 rtc_1: rtc@61 {
349 reg = <0x61>;
350 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]351 sandbox,emul = <&emul1>;
352 };
353
354 i2c_emul: emul {
355 reg = <0xff>;
356 compatible = "sandbox,i2c-emul-parent";
357 emul_eeprom: emul-eeprom {
358 compatible = "sandbox,i2c-eeprom";
359 sandbox,filename = "i2c.bin";
360 sandbox,size = <256>;
361 };
362 emul0: emul0 {
363 compatible = "sandbox,i2c-rtc";
364 };
365 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600[diff] [blame]366 compatible = "sandbox,i2c-rtc";
367 };
368 };
369
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]370 sandbox_pmic: sandbox_pmic {
371 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]372 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]373 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]374
375 mc34708: pmic@41 {
376 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700[diff] [blame]377 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200[diff] [blame]378 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]379 };
380
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100[diff] [blame]381 bootcount@0 {
382 compatible = "u-boot,bootcount-rtc";
383 rtc = <&rtc_1>;
384 offset = <0x13>;
385 };
386
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100[diff] [blame]387 adc@0 {
388 compatible = "sandbox,adc";
389 vdd-supply = <&buck2>;
390 vss-microvolts = <0>;
391 };
392
Simon Glass515dcff2020-02-06 09:55:00 -0700[diff] [blame]393 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700[diff] [blame]394 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700[diff] [blame]395 interrupt-controller;
396 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700[diff] [blame]397 };
398
Simon Glass90b6fef2016-01-18 19:52:26 -0700[diff] [blame]399 lcd {
400 u-boot,dm-pre-reloc;
401 compatible = "sandbox,lcd-sdl";
402 xres = <1366>;
403 yres = <768>;
404 };
405
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]406 leds {
407 compatible = "gpio-leds";
408
409 iracibble {
410 gpios = <&gpio_a 1 0>;
411 label = "sandbox:red";
412 };
413
414 martinet {
415 gpios = <&gpio_a 2 0>;
416 label = "sandbox:green";
417 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200[diff] [blame]418
419 default_on {
420 gpios = <&gpio_a 5 0>;
421 label = "sandbox:default_on";
422 default-state = "on";
423 };
424
425 default_off {
426 gpios = <&gpio_a 6 0>;
427 label = "sandbox:default_off";
428 default-state = "off";
429 };
Simon Glassd783eb32015-07-06 12:54:34 -0600[diff] [blame]430 };
431
Stephen Warren62f2c902016-05-16 17:41:37 -0600[diff] [blame]432 mbox: mbox {
433 compatible = "sandbox,mbox";
434 #mbox-cells = <1>;
435 };
436
437 mbox-test {
438 compatible = "sandbox,mbox-test";
439 mboxes = <&mbox 100>, <&mbox 1>;
440 mbox-names = "other", "test";
441 };
442
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900[diff] [blame]443 cpus {
444 cpu-test1 {
445 compatible = "sandbox,cpu_sandbox";
446 u-boot,dm-pre-reloc;
447 };
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]448
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900[diff] [blame]449 cpu-test2 {
450 compatible = "sandbox,cpu_sandbox";
451 u-boot,dm-pre-reloc;
452 };
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]453
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900[diff] [blame]454 cpu-test3 {
455 compatible = "sandbox,cpu_sandbox";
456 u-boot,dm-pre-reloc;
457 };
Mario Sixdea5df72018-08-06 10:23:44 +0200[diff] [blame]458 };
459
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]460 i2s: i2s {
461 compatible = "sandbox,i2s";
462 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700[diff] [blame]463 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700[diff] [blame]464 };
465
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200[diff] [blame]466 nop-test_0 {
467 compatible = "sandbox,nop_sandbox1";
468 nop-test_1 {
469 compatible = "sandbox,nop_sandbox2";
470 bind = "True";
471 };
472 nop-test_2 {
473 compatible = "sandbox,nop_sandbox2";
474 bind = "False";
475 };
476 };
477
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200[diff] [blame]478 misc-test {
479 compatible = "sandbox,misc_sandbox";
480 };
481
Simon Glasse4fef742017-04-23 20:02:07 -0600[diff] [blame]482 mmc2 {
483 compatible = "sandbox,mmc";
484 };
485
486 mmc1 {
487 compatible = "sandbox,mmc";
488 };
489
490 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600[diff] [blame]491 compatible = "sandbox,mmc";
492 };
493
Simon Glass53a68b32019-02-16 20:24:50 -0700[diff] [blame]494 pch {
495 compatible = "sandbox,pch";
496 };
497
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]498 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]499 compatible = "sandbox,pci";
500 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]501 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]502 #address-cells = <3>;
503 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600[diff] [blame]504 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]505 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]506 pci@0,0 {
507 compatible = "pci-generic";
508 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]509 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700[diff] [blame]510 };
Alex Margineanf1274432019-06-07 11:24:24 +0300[diff] [blame]511 pci@1,0 {
512 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600[diff] [blame]513 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
514 reg = <0x02000814 0 0 0 0
515 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]516 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300[diff] [blame]517 };
Simon Glass937bb472019-12-06 21:41:57 -0700[diff] [blame]518 p2sb-pci@2,0 {
519 compatible = "sandbox,p2sb";
520 reg = <0x02001010 0 0 0 0>;
521 sandbox,emul = <&p2sb_emul>;
522
523 adder {
524 intel,p2sb-port-id = <3>;
525 compatible = "sandbox,adder";
526 };
527 };
Simon Glass8c501022019-12-06 21:41:54 -0700[diff] [blame]528 pci@1e,0 {
529 compatible = "sandbox,pmc";
530 reg = <0xf000 0 0 0 0>;
531 sandbox,emul = <&pmc_emul1e>;
532 acpi-base = <0x400>;
533 gpe0-dwx-mask = <0xf>;
534 gpe0-dwx-shift-base = <4>;
535 gpe0-dw = <6 7 9>;
536 gpe0-sts = <0x20>;
537 gpe0-en = <0x30>;
538 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]539 pci@1f,0 {
540 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600[diff] [blame]541 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
542 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]543 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]544 };
545 };
546
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]547 pci-emul0 {
548 compatible = "sandbox,pci-emul-parent";
549 swap_case_emul0_0: emul0@0,0 {
550 compatible = "sandbox,swap-case";
551 };
552 swap_case_emul0_1: emul0@1,0 {
553 compatible = "sandbox,swap-case";
554 use-ea;
555 };
556 swap_case_emul0_1f: emul0@1f,0 {
557 compatible = "sandbox,swap-case";
558 };
Simon Glass937bb472019-12-06 21:41:57 -0700[diff] [blame]559 p2sb_emul: emul@2,0 {
560 compatible = "sandbox,p2sb-emul";
561 };
Simon Glass8c501022019-12-06 21:41:54 -0700[diff] [blame]562 pmc_emul1e: emul@1e,0 {
563 compatible = "sandbox,pmc-emul";
564 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]565 };
566
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]567 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]568 compatible = "sandbox,pci";
569 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]570 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]571 #address-cells = <3>;
572 #size-cells = <2>;
573 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
574 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700[diff] [blame]575 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200[diff] [blame]576 0x0c 0x00 0x1234 0x5678
577 0x10 0x00 0x1234 0x5678>;
578 pci@10,0 {
579 reg = <0x8000 0 0 0 0>;
580 };
Bin Meng408e5902018-08-03 01:14:41 -0700[diff] [blame]581 };
582
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]583 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]584 compatible = "sandbox,pci";
585 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500[diff] [blame]586 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]587 #address-cells = <3>;
588 #size-cells = <2>;
589 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
590 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
591 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
592 pci@1f,0 {
593 compatible = "pci-generic";
594 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600[diff] [blame]595 sandbox,emul = <&swap_case_emul2_1f>;
596 };
597 };
598
599 pci-emul2 {
600 compatible = "sandbox,pci-emul-parent";
601 swap_case_emul2_1f: emul2@1f,0 {
602 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700[diff] [blame]603 };
604 };
605
Ramon Friedc64f19b2019-04-27 11:15:23 +0300[diff] [blame]606 pci_ep: pci_ep {
607 compatible = "sandbox,pci_ep";
608 };
609
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]610 probing {
611 compatible = "simple-bus";
612 test1 {
613 compatible = "denx,u-boot-probe-test";
614 };
615
616 test2 {
617 compatible = "denx,u-boot-probe-test";
618 };
619
620 test3 {
621 compatible = "denx,u-boot-probe-test";
622 };
623
624 test4 {
625 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]626 first-syscon = <&syscon0>;
627 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100[diff] [blame]628 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600[diff] [blame]629 };
630 };
631
Stephen Warren92c67fa2016-07-13 13:45:31 -0600[diff] [blame]632 pwrdom: power-domain {
633 compatible = "sandbox,power-domain";
634 #power-domain-cells = <1>;
635 };
636
637 power-domain-test {
638 compatible = "sandbox,power-domain-test";
639 power-domains = <&pwrdom 2>;
640 };
641
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]642 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]643 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]644 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]645 };
646
647 pwm2 {
648 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]649 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600[diff] [blame]650 };
651
Simon Glass3d355e62015-07-06 12:54:31 -0600[diff] [blame]652 ram {
653 compatible = "sandbox,ram";
654 };
655
Simon Glassd860f222015-07-06 12:54:29 -0600[diff] [blame]656 reset@0 {
657 compatible = "sandbox,warm-reset";
658 };
659
660 reset@1 {
661 compatible = "sandbox,reset";
662 };
663
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]664 resetc: reset-ctl {
665 compatible = "sandbox,reset-ctl";
666 #reset-cells = <1>;
667 };
668
669 reset-ctl-test {
670 compatible = "sandbox,reset-ctl-test";
671 resets = <&resetc 100>, <&resetc 2>;
672 reset-names = "other", "test";
673 };
674
Sughosh Ganu23e37512019-12-28 23:58:31 +0530[diff] [blame]675 rng {
676 compatible = "sandbox,sandbox-rng";
677 };
678
Nishanth Menonedf85812015-09-17 15:42:41 -0500[diff] [blame]679 rproc_1: rproc@1 {
680 compatible = "sandbox,test-processor";
681 remoteproc-name = "remoteproc-test-dev1";
682 };
683
684 rproc_2: rproc@2 {
685 compatible = "sandbox,test-processor";
686 internal-memory-mapped;
687 remoteproc-name = "remoteproc-test-dev2";
688 };
689
Simon Glass5620cf82018-10-01 12:22:40 -0600[diff] [blame]690 panel {
691 compatible = "simple-panel";
692 backlight = <&backlight 0 100>;
693 };
694
Ramon Fried26ed32e2018-07-02 02:57:59 +0300[diff] [blame]695 smem@0 {
696 compatible = "sandbox,smem";
697 };
698
Simon Glass76072ac2018-12-10 10:37:36 -0700[diff] [blame]699 sound {
700 compatible = "sandbox,sound";
701 cpu {
702 sound-dai = <&i2s 0>;
703 };
704
705 codec {
706 sound-dai = <&audio 0>;
707 };
708 };
709
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]710 spi@0 {
711 #address-cells = <1>;
712 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]713 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]714 compatible = "sandbox,spi";
715 cs-gpios = <0>, <&gpio_a 0>;
716 spi.bin@0 {
717 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]718 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]719 spi-max-frequency = <40000000>;
720 sandbox,filename = "spi.bin";
721 };
722 };
723
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]724 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]725 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200[diff] [blame]726 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]727 };
728
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100[diff] [blame]729 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]730 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600[diff] [blame]731 reg = <0x20 5
732 0x28 6
733 0x30 7
734 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600[diff] [blame]735 };
736
Patrick Delaunayee010432019-03-07 09:57:13 +0100[diff] [blame]737 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900[diff] [blame]738 compatible = "simple-mfd", "syscon";
739 reg = <0x40 5
740 0x48 6
741 0x50 7
742 0x58 8>;
743 };
744
Thomas Chou6f2cfbf2015-12-11 16:27:34 +0800[diff] [blame]745 timer {
746 compatible = "sandbox,timer";
747 clock-frequency = <1000000>;
748 };
749
Miquel Raynal80938c12018-05-15 11:57:27 +0200[diff] [blame]750 tpm2 {
751 compatible = "sandbox,tpm2";
752 };
753
Simon Glass5b968632015-05-22 15:42:15 -0600[diff] [blame]754 uart0: serial {
755 compatible = "sandbox,serial";
756 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]757 };
758
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]759 usb_0: usb@0 {
760 compatible = "sandbox,usb";
761 status = "disabled";
762 hub {
763 compatible = "sandbox,usb-hub";
764 #address-cells = <1>;
765 #size-cells = <0>;
766 flash-stick {
767 reg = <0>;
768 compatible = "sandbox,usb-flash";
769 };
770 };
771 };
772
773 usb_1: usb@1 {
774 compatible = "sandbox,usb";
775 hub {
776 compatible = "usb-hub";
777 usb,device-class = <9>;
778 hub-emul {
779 compatible = "sandbox,usb-hub";
780 #address-cells = <1>;
781 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]782 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]783 reg = <0>;
784 compatible = "sandbox,usb-flash";
785 sandbox,filepath = "testflash.bin";
786 };
787
Simon Glass4700fe52015-11-08 23:48:01 -0700[diff] [blame]788 flash-stick@1 {
789 reg = <1>;
790 compatible = "sandbox,usb-flash";
791 sandbox,filepath = "testflash1.bin";
792 };
793
794 flash-stick@2 {
795 reg = <2>;
796 compatible = "sandbox,usb-flash";
797 sandbox,filepath = "testflash2.bin";
798 };
799
Simon Glassc0ccc722015-11-08 23:48:08 -0700[diff] [blame]800 keyb@3 {
801 reg = <3>;
802 compatible = "sandbox,usb-keyb";
803 };
804
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]805 };
806 };
807 };
808
809 usb_2: usb@2 {
810 compatible = "sandbox,usb";
811 status = "disabled";
812 };
813
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]814 spmi: spmi@0 {
815 compatible = "sandbox,spmi";
816 #address-cells = <0x1>;
817 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600[diff] [blame]818 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]819 pm8916@0 {
820 compatible = "qcom,spmi-pmic";
821 reg = <0x0 0x1>;
822 #address-cells = <0x1>;
823 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -0600[diff] [blame]824 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +0200[diff] [blame]825
826 spmi_gpios: gpios@c000 {
827 compatible = "qcom,pm8916-gpio";
828 reg = <0xc000 0x400>;
829 gpio-controller;
830 gpio-count = <4>;
831 #gpio-cells = <2>;
832 gpio-bank-name="spmi";
833 };
834 };
835 };
maxims@google.comdaea6d42017-04-17 12:00:21 -0700[diff] [blame]836
837 wdt0: wdt@0 {
838 compatible = "sandbox,wdt";
839 };
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]840
Mario Six95922152018-08-09 14:51:19 +0200[diff] [blame]841 axi: axi@0 {
842 compatible = "sandbox,axi";
843 #address-cells = <0x1>;
844 #size-cells = <0x1>;
845 store@0 {
846 compatible = "sandbox,sandbox_store";
847 reg = <0x0 0x400>;
848 };
849 };
850
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]851 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -0700[diff] [blame]852 #address-cells = <1>;
853 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -0700[diff] [blame]854 setting = "sunrise ohoka";
855 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -0700[diff] [blame]856 int-values = <0x1937 72993>;
Rob Clarka471b672018-01-10 11:33:30 +0100[diff] [blame]857 chosen-test {
858 compatible = "denx,u-boot-fdt-test";
859 reg = <9 1>;
860 };
861 };
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]862
863 translation-test@8000 {
864 compatible = "simple-bus";
865 reg = <0x8000 0x4000>;
866
867 #address-cells = <0x2>;
868 #size-cells = <0x1>;
869
870 ranges = <0 0x0 0x8000 0x1000
871 1 0x100 0x9000 0x1000
872 2 0x200 0xA000 0x1000
873 3 0x300 0xB000 0x1000
874 >;
875
Fabien Dessenne22236e02019-05-31 15:11:30 +0200[diff] [blame]876 dma-ranges = <0 0x000 0x10000000 0x1000
877 1 0x100 0x20000000 0x1000
878 >;
879
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]880 dev@0,0 {
881 compatible = "denx,u-boot-fdt-dummy";
882 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +0100[diff] [blame]883 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +0100[diff] [blame]884 };
885
886 dev@1,100 {
887 compatible = "denx,u-boot-fdt-dummy";
888 reg = <1 0x100 0x1000>;
889
890 };
891
892 dev@2,200 {
893 compatible = "denx,u-boot-fdt-dummy";
894 reg = <2 0x200 0x1000>;
895 };
896
897
898 noxlatebus@3,300 {
899 compatible = "simple-bus";
900 reg = <3 0x300 0x1000>;
901
902 #address-cells = <0x1>;
903 #size-cells = <0x0>;
904
905 dev@42 {
906 compatible = "denx,u-boot-fdt-dummy";
907 reg = <0x42>;
908 };
909 };
910 };
Mario Six02ad6fb2018-09-27 09:19:31 +0200[diff] [blame]911
912 osd {
913 compatible = "sandbox,sandbox_osd";
914 };
Tom Rinib93eea72018-09-30 18:16:51 -0400[diff] [blame]915
Mario Sixab664ff2018-07-31 11:44:13 +0200[diff] [blame]916 board {
917 compatible = "sandbox,board_sandbox";
918 };
Jens Wiklander86afaa62018-09-25 16:40:16 +0200[diff] [blame]919
920 sandbox_tee {
921 compatible = "sandbox,tee";
922 };
Bin Meng1bb290d2018-10-15 02:21:26 -0700[diff] [blame]923
924 sandbox_virtio1 {
925 compatible = "sandbox,virtio1";
926 };
927
928 sandbox_virtio2 {
929 compatible = "sandbox,virtio2";
930 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200[diff] [blame]931
932 pinctrl {
933 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +0100[diff] [blame]934
935 pinctrl-names = "default";
936 pinctrl-0 = <&gpios>;
937
938 gpios: gpios {
939 gpio0 {
940 pins = "GPIO0";
941 bias-pull-up;
942 input-disable;
943 };
944 gpio1 {
945 pins = "GPIO1";
946 output-high;
947 drive-open-drain;
948 };
949 gpio2 {
950 pins = "GPIO2";
951 bias-pull-down;
952 input-enable;
953 };
954 gpio3 {
955 pins = "GPIO3";
956 bias-disable;
957 };
958 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +0200[diff] [blame]959 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +0100[diff] [blame]960
961 hwspinlock@0 {
962 compatible = "sandbox,hwspinlock";
963 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]964
965 dma: dma {
966 compatible = "sandbox,dma";
967 #dma-cells = <1>;
968
969 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
970 dma-names = "m2m", "tx0", "rx0";
971 };
Alex Marginean0daa53a2019-06-03 19:12:28 +0300[diff] [blame]972
Alex Marginean0649be52019-07-12 10:13:53 +0300[diff] [blame]973 /*
974 * keep mdio-mux ahead of mdio so that the mux is removed first at the
975 * end of the test. If parent mdio is removed first, clean-up of the
976 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
977 * active at the end of the test. That it turn doesn't allow the mdio
978 * class to be destroyed, triggering an error.
979 */
980 mdio-mux-test {
981 compatible = "sandbox,mdio-mux";
982 #address-cells = <1>;
983 #size-cells = <0>;
984 mdio-parent-bus = <&mdio>;
985
986 mdio-ch-test@0 {
987 reg = <0>;
988 };
989 mdio-ch-test@1 {
990 reg = <1>;
991 };
992 };
993
994 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +0300[diff] [blame]995 compatible = "sandbox,mdio";
996 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]997};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]998
999#include "sandbox_pmic.dtsi"