| Hou Zhiqiang | 224999f | 2019-08-20 09:35:28 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| 2 | /* |
| 3 | * P1020 Silicon/SoC Device Tree Source (post include) |
| 4 | * |
| 5 | * Copyright 2013 Freescale Semiconductor Inc. |
| 6 | * Copyright 2019 NXP |
| 7 | */ |
| 8 | |
| 9 | &soc { |
| 10 | #address-cells = <1>; |
| 11 | #size-cells = <1>; |
| 12 | device_type = "soc"; |
| 13 | compatible = "fsl,p1020-immr", "simple-bus"; |
| 14 | bus-frequency = <0x0>; |
| 15 | |
| Ran Wang | 6225824 | 2019-12-12 17:30:53 +0800 | [diff] [blame] | 16 | usb@22000 { |
| 17 | compatible = "fsl-usb2-dr"; |
| 18 | reg = <0x22000 0x1000>; |
| 19 | phy_type = "ulpi"; |
| 20 | }; |
| 21 | |
| 22 | usb@23000 { |
| 23 | compatible = "fsl-usb2-dr"; |
| 24 | reg = <0x23000 0x1000>; |
| 25 | phy_type = "ulpi"; |
| 26 | }; |
| 27 | |
| Hou Zhiqiang | 224999f | 2019-08-20 09:35:28 +0000 | [diff] [blame] | 28 | mpic: pic@40000 { |
| 29 | interrupt-controller; |
| 30 | #address-cells = <0>; |
| 31 | #interrupt-cells = <4>; |
| 32 | reg = <0x40000 0x40000>; |
| 33 | compatible = "fsl,mpic"; |
| 34 | device_type = "open-pic"; |
| 35 | big-endian; |
| 36 | single-cpu-affinity; |
| 37 | last-interrupt-source = <255>; |
| 38 | }; |
| Yinbo Zhu | a03609c | 2019-10-15 17:20:40 +0800 | [diff] [blame] | 39 | |
| 40 | esdhc: esdhc@2e000 { |
| 41 | compatible = "fsl,esdhc"; |
| 42 | reg = <0x2e000 0x1000>; |
| 43 | /* Filled in by U-Boot */ |
| 44 | clock-frequency = <0>; |
| 45 | }; |
| Ran Wang | 6225824 | 2019-12-12 17:30:53 +0800 | [diff] [blame] | 46 | |
| Hou Zhiqiang | 224999f | 2019-08-20 09:35:28 +0000 | [diff] [blame] | 47 | }; |
| Hou Zhiqiang | 802865c | 2019-08-27 11:04:04 +0000 | [diff] [blame] | 48 | |
| 49 | /* PCIe controller base address 0x9000 */ |
| 50 | &pci1 { |
| 51 | compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; |
| 52 | law_trgt_if = <1>; |
| 53 | #address-cells = <3>; |
| 54 | #size-cells = <2>; |
| 55 | device_type = "pci"; |
| 56 | bus-range = <0x0 0xff>; |
| 57 | }; |
| 58 | |
| 59 | /* PCIe controller base address 0xa000 */ |
| 60 | &pci0 { |
| 61 | compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; |
| 62 | law_trgt_if = <2>; |
| 63 | #address-cells = <3>; |
| 64 | #size-cells = <2>; |
| 65 | device_type = "pci"; |
| 66 | bus-range = <0x0 0xff>; |
| 67 | }; |