blob: 77d4f8e47f74cc43d4f6154f1887be20765a732c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Christophe Leroy069fa832017-07-06 10:23:22 +02002/*
3 * (C) Copyright 2000-2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Christophe Leroy069fa832017-07-06 10:23:22 +02005 */
6
7#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -07008#include <clock_legacy.h>
Christophe Leroy069fa832017-07-06 10:23:22 +02009#include <mpc8xx.h>
10#include <asm/processor.h>
Christophe Leroy394f9b32017-07-06 10:33:13 +020011#include <asm/io.h>
Christophe Leroy069fa832017-07-06 10:23:22 +020012
13DECLARE_GLOBAL_DATA_PTR;
14
Christophe Leroy069fa832017-07-06 10:23:22 +020015/*
16 * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
17 */
Christophe Leroy48f896d2017-07-06 10:33:17 +020018int get_clocks(void)
Christophe Leroy069fa832017-07-06 10:23:22 +020019{
Christophe Leroy5c59bdf2018-03-16 17:20:33 +010020 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
Christophe Leroy394f9b32017-07-06 10:33:13 +020021 uint sccr = in_be32(&immap->im_clkrst.car_sccr);
Christophe Leroy297cbac2017-07-13 15:09:44 +020022 uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2);
23
Christophe Leroy069fa832017-07-06 10:23:22 +020024 /*
25 * If for some reason measuring the gclk frequency won't
26 * work, we return the hardwired value.
27 * (For example, the cogent CMA286-60 CPU module has no
28 * separate oscillator for PITRTCLK)
29 */
30 gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
31
32 if ((sccr & SCCR_EBDF11) == 0) {
33 /* No Bus Divider active */
34 gd->bus_clk = gd->cpu_clk;
35 } else {
36 /* The MPC8xx has only one BDF: half clock speed */
37 gd->bus_clk = gd->cpu_clk / 2;
38 }
39
Christophe Leroy297cbac2017-07-13 15:09:44 +020040 gd->arch.brg_clk = gd->cpu_clk / divider;
Christophe Leroy069fa832017-07-06 10:23:22 +020041
Christophe Leroy48f896d2017-07-06 10:33:17 +020042 return 0;
Christophe Leroy069fa832017-07-06 10:23:22 +020043}