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git01.mediatek.com / filogic / uboot / a46d821fc88674246b74569dcdc54cdac91dfc4c / . / post / cpu / asm.S
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wdenka46d8212002-09-12 22:01:13 +0000[diff] [blame^]1/*
2 * Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <config.h>
24
25#ifdef CONFIG_POST
26
27#include <post.h>
28#include <ppc_asm.tmpl>
29#include <ppc_defs.h>
30#include <asm/cache.h>
31
32#if CONFIG_POST & CFG_POST_CPU
33
34/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */
35 .global cpu_post_exec_02
36cpu_post_exec_02:
37 mflr r0
38 stwu r0, -4(r1)
39
40 subi r1, r1, 104
41 stmw r6, 0(r1)
42
43 mtlr r3
44 mr r3, r4
45 mr r4, r5
46 blrl
47
48 lmw r6, 0(r1)
49 addi r1, r1, 104
50
51 lwz r0, 0(r1)
52 addi r1, r1, 4
53 mtlr r0
54 blr
55
56/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */
57 .global cpu_post_exec_04
58cpu_post_exec_04:
59 mflr r0
60 stwu r0, -4(r1)
61
62 subi r1, r1, 96
63 stmw r8, 0(r1)
64
65 mtlr r3
66 mr r3, r4
67 mr r4, r5
68 mr r5, r6
69 mtxer r7
70 blrl
71
72 lmw r8, 0(r1)
73 addi r1, r1, 96
74
75 lwz r0, 0(r1)
76 addi r1, r1, 4
77 mtlr r0
78 blr
79
80/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */
81 .global cpu_post_exec_12
82cpu_post_exec_12:
83 mflr r0
84 stwu r0, -4(r1)
85 stwu r4, -4(r1)
86
87 mtlr r3
88 mr r3, r5
89 mr r4, r6
90 blrl
91
92 lwz r4, 0(r1)
93 stw r3, 0(r4)
94
95 lwz r0, 4(r1)
96 addi r1, r1, 8
97 mtlr r0
98 blr
99
100/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */
101 .global cpu_post_exec_11
102cpu_post_exec_11:
103 mflr r0
104 stwu r0, -4(r1)
105 stwu r4, -4(r1)
106
107 mtlr r3
108 mr r3, r5
109 blrl
110
111 lwz r4, 0(r1)
112 stw r3, 0(r4)
113
114 lwz r0, 4(r1)
115 addi r1, r1, 8
116 mtlr r0
117 blr
118
119/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */
120 .global cpu_post_exec_21
121cpu_post_exec_21:
122 mflr r0
123 stwu r0, -4(r1)
124 stwu r4, -4(r1)
125 stwu r5, -4(r1)
126
127 li r0, 0
128 mtxer r0
129 lwz r0, 0(r4)
130 mtcr r0
131
132 mtlr r3
133 mr r3, r6
134 blrl
135
136 mfcr r0
137 lwz r4, 4(r1)
138 stw r0, 0(r4)
139 lwz r4, 0(r1)
140 stw r3, 0(r4)
141
142 lwz r0, 8(r1)
143 addi r1, r1, 12
144 mtlr r0
145 blr
146
147/* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
148 ulong op2); */
149 .global cpu_post_exec_22
150cpu_post_exec_22:
151 mflr r0
152 stwu r0, -4(r1)
153 stwu r4, -4(r1)
154 stwu r5, -4(r1)
155
156 li r0, 0
157 mtxer r0
158 lwz r0, 0(r4)
159 mtcr r0
160
161 mtlr r3
162 mr r3, r6
163 mr r4, r7
164 blrl
165
166 mfcr r0
167 lwz r4, 4(r1)
168 stw r0, 0(r4)
169 lwz r4, 0(r1)
170 stw r3, 0(r4)
171
172 lwz r0, 8(r1)
173 addi r1, r1, 12
174 mtlr r0
175 blr
176
177/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */
178 .global cpu_post_exec_12w
179cpu_post_exec_12w:
180 mflr r0
181 stwu r0, -4(r1)
182 stwu r4, -4(r1)
183
184 mtlr r3
185 lwz r3, 0(r4)
186 mr r4, r5
187 mr r5, r6
188 blrl
189
190 lwz r4, 0(r1)
191 stw r3, 0(r4)
192
193 lwz r0, 4(r1)
194 addi r1, r1, 8
195 mtlr r0
196 blr
197
198/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */
199 .global cpu_post_exec_11w
200cpu_post_exec_11w:
201 mflr r0
202 stwu r0, -4(r1)
203 stwu r4, -4(r1)
204
205 mtlr r3
206 lwz r3, 0(r4)
207 mr r4, r5
208 blrl
209
210 lwz r4, 0(r1)
211 stw r3, 0(r4)
212
213 lwz r0, 4(r1)
214 addi r1, r1, 8
215 mtlr r0
216 blr
217
218/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */
219 .global cpu_post_exec_22w
220cpu_post_exec_22w:
221 mflr r0
222 stwu r0, -4(r1)
223 stwu r4, -4(r1)
224 stwu r6, -4(r1)
225
226 mtlr r3
227 lwz r3, 0(r4)
228 mr r4, r5
229 blrl
230
231 lwz r4, 4(r1)
232 stw r3, 0(r4)
233 lwz r4, 0(r1)
234 stw r5, 0(r4)
235
236 lwz r0, 8(r1)
237 addi r1, r1, 12
238 mtlr r0
239 blr
240
241/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */
242 .global cpu_post_exec_21w
243cpu_post_exec_21w:
244 mflr r0
245 stwu r0, -4(r1)
246 stwu r4, -4(r1)
247 stwu r5, -4(r1)
248
249 mtlr r3
250 lwz r3, 0(r4)
251 blrl
252
253 lwz r5, 4(r1)
254 stw r3, 0(r5)
255 lwz r5, 0(r1)
256 stw r4, 0(r5)
257
258 lwz r0, 8(r1)
259 addi r1, r1, 12
260 mtlr r0
261 blr
262
263/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */
264 .global cpu_post_exec_21x
265cpu_post_exec_21x:
266 mflr r0
267 stwu r0, -4(r1)
268 stwu r4, -4(r1)
269 stwu r5, -4(r1)
270
271 mtlr r3
272 mr r3, r6
273 blrl
274
275 lwz r5, 4(r1)
276 stw r3, 0(r5)
277 lwz r5, 0(r1)
278 stw r4, 0(r5)
279
280 lwz r0, 8(r1)
281 addi r1, r1, 12
282 mtlr r0
283 blr
284
285/* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
286 ulong cr); */
287 .global cpu_post_exec_31
288cpu_post_exec_31:
289 mflr r0
290 stwu r0, -4(r1)
291 stwu r4, -4(r1)
292 stwu r5, -4(r1)
293 stwu r6, -4(r1)
294
295 mtlr r3
296 lwz r3, 0(r4)
297 lwz r4, 0(r5)
298 mr r6, r7
299 blrl
300
301 lwz r7, 8(r1)
302 stw r3, 0(r7)
303 lwz r7, 4(r1)
304 stw r4, 0(r7)
305 lwz r7, 0(r1)
306 stw r5, 0(r7)
307
308 lwz r0, 12(r1)
309 addi r1, r1, 16
310 mtlr r0
311 blr
312
313/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */
314 .global cpu_post_complex_1_asm
315cpu_post_complex_1_asm:
316 li r9,0
317 cmpw r9,r7
318 bge cpu_post_complex_1_done
319 mtctr r7
320cpu_post_complex_1_loop:
321 mullw r0,r3,r4
322 subf r0,r5,r0
323 divw r0,r0,r6
324 add r9,r9,r0
325 bdnz cpu_post_complex_1_loop
326cpu_post_complex_1_done:
327 mr r3,r9
328 blr
329
330/* int cpu_post_complex_2_asm (int x, int n); */
331 .global cpu_post_complex_2_asm
332cpu_post_complex_2_asm:
333 mr. r0,r4
334 mtctr r0
335 mr r0,r3
336 li r3,1
337 li r4,1
338 blelr
339cpu_post_complex_2_loop:
340 mullw r3,r3,r0
341 add r3,r3,r4
342 bdnz cpu_post_complex_2_loop
343blr
344
345#endif
346#endif